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| Features * High-performance, Low-power AVR(R) 8-bit Microcontroller - 130 Powerful Instructions - Most Single Clock Cycle Execution - 32 x 8 General Purpose Working Registers - Fully Static Operation - Up to 8 MIPS Throughput at 8 MHz - On-chip 2-cycle Multiplier Nonvolatile Program and Data Memories Self-programming In-System Programmable Flash Memory - 16K Bytes with Optional Boot Block (256 - 2K Bytes) Endurance: 1,000 Write/Erase Cycles - Boot Section Allows Reprogramming of Program Code without External Programmer - Optional Boot Code Section with Independent Lock Bits - 512 Bytes EEPROM Endurance: 100,000 Write/Erase Cycles - 1024 Bytes Internal SRAM - Programming Lock for Software Security Peripheral Features - Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode - One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode - Real Time Clock with Separate Oscillator and Counter Mode - Three PWM Channels - 8-channel, 10-bit ADC - Byte-oriented Two-wire Serial Interface - Programmable Serial UART - Master/Slave SPI Serial Interface - Programmable Watchdog Timer with Separate On-chip Oscillator - Analog Comparator Special Microcontroller Features - Power-on Reset and Programmable Brown-out Detection - Internal Calibrated RC Oscillator - External and Internal Interrupt Sources - Four Sleep Modes: Idle, ADC Noise Reduction, Power-save, and Power-down Power Consumption at 4 MHz, 3.0V, 25C - Active 5.0 mA - Idle Mode 1.9 mA - Power-down Mode < 1 A I/O and Packages - 32 Programmable I/O Lines - 40-pin PDIP and 44-pin TQFP Operating Voltages - 2.7 - 5.5V for ATMEGA163L - 4.0 - 5.5V for ATMEGA163 Speed Grades - 0 - 4 MHz for ATMEGA163L - 0 - 8 MHz for ATMEGA163 * * * 8-bit Microcontroller with 16K Bytes In-System Programmable Flash ATMEGA163 ATMEGA163L * * Not Recommend for New Designs. Use ATmega16. * * * Rev. 1142E-AVR-02/03 1 Pin Configurations (SCL) (SDA) (SDA) (SCL) 2 ATMEGA163(L) 1142E-AVR-02/03 ATMEGA163(L) Description The ATMEGA163 is a low-power CMOS 8-bit microcontroller based on the AVR architecture. By executing powerful instructions in a single clock cycle, the ATMEGA163 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. Figure 1. Block Diagram PA0 - PA7 PC0 - PC7 Block Diagram VCC PORTA DRIVERS PORTC DRIVERS GND DATA REGISTER PORTA DATA DIR. REG. PORTA DATA REGISTER PORTC DATA DIR. REG. PORTC 8-BIT DATA BUS AVCC ANALOG MUX AGND AREF ADC 2-WIRE SERIAL INTERFACE INTERNAL REFERENCE INTERNAL OSCILLATOR OSCILLATOR XTAL1 OSCILLATOR PROGRAM COUNTER STACK POINTER WATCHDOG TIMER TIMING AND CONTROL XTAL2 RESET PROGRAM FLASH SRAM MCU CONTROL REGISTER INSTRUCTION REGISTER GENERAL PURPOSE REGISTERS X Y Z TIMER/ COUNTERS INSTRUCTION DECODER INTERRUPT UNIT CONTROL LINES ALU EEPROM STATUS REGISTER INTERNAL CALIBRATED OSCILLATOR PROGRAMMING LOGIC SPI UART ANALOG COMPARATOR DATA REGISTER PORTB DATA DIR. REG. PORTB DATA REGISTER PORTD DATA DIR. REG. PORTD + - PORTB DRIVERS PORTD DRIVERS PB0 - PB7 PD0 - PD7 The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock 3 1142E-AVR-02/03 cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. The ATMEGA163 provides the following features: 16K bytes of In-System Self-Programmable Flash, 512 bytes EEPROM, 1024 bytes SRAM, 32 general purpose I/O lines, 32 general purpose working registers, three flexible Timer/Counters with compare modes, internal and external interrupts, a byte oriented Two-wire Serial Interface, an 8-channel, 10-bit ADC, a programmable Watchdog Timer with internal Oscillator, a programmable serial UART, an SPI serial port, and four software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next interrupt or Hardware Reset. In Power-save mode, the asynchronous Timer Oscillator continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modules except asynchronous timer and ADC, to minimize switching noise during ADC conversions. The On-chip ISP Flash can be programmed through an SPI serial interface or a conventional programmer. By installing a Self-Programming Boot Loader, the microcontroller can be updated within the application without any external components. The Boot Program can use any interface to download the application program in the Application Flash memory. By combining an 8-bit CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATMEGA163 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. The ATMEGA163 AVR is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, In-Circuit Emulators, and evaluation kits. Pin Descriptions VCC GND Port A (PA7..PA0) Digital supply voltage. Digital ground. Port A serves as the analog inputs to the A/D Converter. Port A also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used. Port pins can provide internal pull-up resistors (selected for each bit). The Port A output buffers can sink 20mA and can drive LED displays directly. When pins PA0 to PA7 are used as inputs and are externally pulled low, they will source current if the internal pullup resistors are activated. The Port A pins are tristated when a reset condition becomes active, even if the clock is not running. Port B (PB7..PB0) Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers can sink 20 mA. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. Port B also serves the functions of various special features of the ATmega83/163 as listed on page 117. The Port B pins are tristated when a reset condition becomes active, even if the clock is not running. Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port C output buffers can sink 20 mA. As inputs, Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The Port C pins are tristated when a reset condition becomes active, even if the clock is not running. Port C (PC7..PC0) 4 ATMEGA163(L) 1142E-AVR-02/03 ATMEGA163(L) Port C also serves the functions of various special features of the ATMEGA163 as listed on page 124. Port D (PD7..PD0) Port D is an 8-bit bidirectional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers can sink 20 mA. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. Port D also serves the functions of various special features of the ATMEGA163 as listed on page 128. The Port D pins are tristated when a reset condition becomes active, even if the clock is not running. Reset input. A low level on this pin for more than 500 ns will generate a Reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a Reset. Input to the inverting Oscillator amplifier and input to the internal clock operating circuit. Output from the inverting Oscillator amplifier. This is the supply voltage pin for Port A and the A/D Converter. It should be externally connected to VCC, even if the ADC is not used. If the ADC is used, it should be connected to VCC through a low-pass filter. See page 105 for details on operation of the ADC. AREF is the analog reference input pin for the A/D Converter. For ADC operations, a voltage in the range 2.5V to AVCC can be applied to this pin. Analog ground. If the board has a separate analog ground plane, this pin should be connected to this ground plane. Otherwise, connect to GND. The device has the following clock source options, selectable by Flash Fuse bits as shown: Table 1. Device Clocking Options Select(1) Device Clocking Option External Crystal/Ceramic Resonator External Low-frequency Crystal External RC Oscillator Internal RC Oscillator External Clock Note: 1. "1" means unprogrammed, "0" means programmed. CKSEL3..0 1111 - 1010 1001 - 1000 0111 - 0101 0100 - 0010 0001 - 0000 RESET XTAL1 XTAL2 AVCC AREF AGND Clock Options The various choices for each clocking option give different start-up times as shown in Table 5 on page 25. Internal RC Oscillator The internal RC Oscillator option is an On-chip Oscillator running at a fixed frequency of nominally 1 MHz. If selected, the device can operate with no external components. The device is shipped with this option selected. See "EEPROM Read/Write Access" on page 62 for information on calibrating this Oscillator. 5 1142E-AVR-02/03 Crystal Oscillator XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which can be configured for use as an On-chip Oscillator, as shown in Figure 2. Either a quartz crystal or a ceramic resonator may be used. Figure 2. Oscillator Connections External Clock To drive the device from an external clock source, XTAL1 should be driven as shown in Figure 3. Figure 3. External Clock Drive Configuration External RC Oscillator For timing insensitive applications, the external RC configuration shown in Figure 4 can be used. For details on how to choose R and C, see Table 64 on page 162. Figure 4. External RC Configuration VCC NC R XTAL2 XTAL1 C GND Timer Oscillator For the Timer Oscillator pins, TOSC1 and TOSC2, the crystal is connected directly between the pins. No external capacitors are needed. The Oscillator is optimized for use with a 32,768 Hz watch crystal. Applying an external clock source to the TOSC1 pin is not recommended. 6 ATMEGA163(L) 1142E-AVR-02/03 ATMEGA163(L) Architectural Overview The fast-access Register File concept contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This means that during one single clock cycle, one Arithmetic Logic Unit (ALU) operation is executed. Two operands are output from the Register File, the operation is executed, and the result is stored back in the Register File - in one clock cycle. Six of the 32 registers can be used as three 16-bits indirect address register pointers for Data Space addressing - enabling efficient address calculations. One of the three address pointers is also used as the address pointer for look-up tables in Flash Program memory. These added function registers are the 16-bits X-, Y-, and Z-register. The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single register operations are also executed in the ALU. Figure 5 shows the ATMEGA163 AVR Enhanced RISC microcontroller architecture. In addition to the register operation, the conventional Memory Addressing modes can be used on the Register File as well. This is enabled by the fact that the Register File is assigned the 32 lowest Data Space addresses ($00 - $1F), allowing them to be accessed as though they were ordinary memory locations. The I/O Memory space contains 64 addresses for CPU peripheral functions as Control Registers, Timer/Counters, A/D-converters, and other I/O functions. The I/O Memory can be accessed directly, or as the Data Space locations following those of the Register File, $20 - $5F. 7 1142E-AVR-02/03 Figure 5. The ATMEGA163 AVR RISC Architecture Data Bus 8-bit Interrupt Unit 8K X 16 Program Memory Program Counter Status and Control SPI Unit Serial UART Two-wire Serial Interface Instruction Register 32 x 8 General Purpose Registrers Indirect Addressing Instruction Decoder Direct Addressing ALU 8-bit Timer/Counter 16-bit Timer/Counter with PWM 8-bit Timer/Counter with PWM Watchdog Timer Control Lines 1024 x 8 Data SRAM 512 x 8 EEPROM A/D Converter 32 I/O Lines Analog Comparator The AVR uses a Harvard architecture concept - with separate memories and buses for program and data. The Program memory is executed with a two stage pipeline. While one instruction is being executed, the next instruction is pre-fetched from the Program memory. This concept enables instructions to be executed in every clock cycle. The Program memory is In-System Re-programmable Flash memory. With the jump and call instructions, the whole 8K word address space is directly accessed. Most AVR instructions have a single 16-bit word format. Every program memory address contains a 16- or 32-bit instruction. Program Flash memory space is divided in two sections, the Boot Program section (256 to 2,048 bytes, see page 134) and the Application Program section. Both sections have dedicated Lock bits for write and read/write protection. The SPM instruction that writes into the Application Flash memory section is allowed only in the Boot Program section. During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the Stack. The Stack is effectively allocated in the general data SRAM, and consequently the Stack size is only limited by the total SRAM size and the usage of the SRAM. All user programs must initialize the SP in the reset routine (before subroutines or interrupts are executed). The 11-bit Stack Pointer SP is read/write accessible in the I/O space. 8 ATMEGA163(L) 1142E-AVR-02/03 ATMEGA163(L) The 1,024 bytes data SRAM can be easily accessed through the five different addressing modes supported in the AVR architecture. The memory spaces in the AVR architecture are all linear and regular memory maps. A flexible interrupt module has its Control Registers in the I/O space with an additional Global Interrupt Enable bit in the Status Register. All interrupts have a separate Interrupt Vector in the Interrupt Vector table at the beginning of the Program memory. The interrupts have priority in accordance with their Interrupt Vector position. The lower the Interrupt Vector address, the higher the priority. Figure 6. Memory Maps Program Memory $0000 Application Flash Section Boot Flash Section $1FFF 9 1142E-AVR-02/03 The General Purpose Register File Figure 7 shows the structure of the 32 general purpose working registers in the CPU. Figure 7. AVR CPU General Purpose Working Registers 7 R0 R1 R2 ... R13 General Purpose Working Registers R14 R15 R16 R17 ... R26 R27 R28 R29 R30 R31 $1A $1B $1C $1D $1E $1F X-register Low Byte X-register High Byte Y-register Low Byte Y-register High Byte Z-register Low Byte Z-register High Byte $0D $0E $0F $10 $11 0 Addr. $00 $01 $02 All the register operating instructions in the instruction set have direct and single cycle access to all registers. The only exception is the five constant arithmetic and logic instructions SBCI, SUBI, CPI, ANDI, and ORI between a constant and a register, and the LDI instruction for load immediate constant data. These instructions apply to the second half of the registers in the Register File - R16..R31. The general SBC, SUB, CP, AND, and OR and all other operations between two registers or on a single register apply to the entire Register File. As shown in Figure 7, each register is also assigned a data memory address, mapping them directly into the first 32 locations of the user Data Space. Although not being physically implemented as SRAM locations, this memory organization provides great flexibility in access of the registers, as the X-, Y-, and Z-registers can be set to index any register in the file. The X-register, Y-register, and Z-register The registers R26..R31 have some added functions to their general purpose usage. These registers are address pointers for indirect addressing of the Data Space. The three indirect address registers X, Y, and Z are defined as: Figure 8. The X-, Y-, and Z-registers 15 X - register 7 R27 ($1B) XH 0 XL 7 R26 ($1A) 0 0 15 Y - register 7 R29 ($1D) 15 Z - register 7 R31 ($1F) YH 0 YL 7 R28 ($1C) 0 0 ZH 0 ZL 7 R30 ($1E) 0 0 10 ATMEGA163(L) 1142E-AVR-02/03 ATMEGA163(L) In the different addressing modes these address registers have functions as fixed displacement, automatic increment and decrement (see the descriptions for the different instructions). The ALU - Arithmetic Logic Unit The high-performance AVR ALU operates in direct connection with all the 32 general purpose working registers. Within a single clock cycle, ALU operations between registers in the Register File are executed. The ALU operations are divided into three main categories - arithmetic, logical, and bit-functions. ATMEGA163 also provides a powerful multiplier supporting both signed/unsigned multiplication and fractional format. See the Instruction Set section for a detailed description. The ATMEGA163 contains 16K bytes On-chip In-System Self-Programmable Flash memory for program storage. Since all instructions are 16- or 32-bit words, the Flash is organized as 8K x 16. The Flash Program memory space is divided in two sections, Boot Program section and Application Program section. The Flash memory has an endurance of at least 1,000 write/erase cycles. The ATMEGA163 Program Counter (PC) is 13 bits wide, thus addressing the 8,192 Program Memory locations. The operation of Boot Program section and associated Boot Lock bits for software protection are described in detail on page 134. See also page 154 for a detailed description on Flash data serial downloading. Constant tables can be allocated within the entire Program Memory address space (see the LPM - Load Program Memory instruction description). See also page 12 for the different Program Memory Addressing modes. The In-System SelfProgrammable Flash Program Memory The SRAM Data Memory Figure 9 shows how the ATMEGA163 SRAM Memory is organized. Figure 9. SRAM Organization Register File R0 R1 R2 ... R29 R30 R31 I/O Registers $00 $01 $02 ... $3D $3E $3F Data Address Space $0000 $0001 $0002 ... $001D $001E $001F $0020 $0021 $0022 ... $005D $005E $005F Internal SRAM $0060 $0061 ... $045E $045F 11 1142E-AVR-02/03 The lower 1,120 Data Memory locations address the Register File, the I/O Memory, and the internal data SRAM. The first 96 locations address the Register File + I/O Memory, and the next 1,024 locations address the internal data SRAM. The five different addressing modes for the data memory cover: Direct, Indirect with Displacement, Indirect, Indirect with Pre-decrement, and Indirect with Post-increment. In the Register File, registers R26 to R31 feature the indirect Addressing Pointer Registers. The direct addressing reaches the entire data space. The Indirect with Displacement mode features a 63 address locations reach from the base address given by the Y- or Z-register. When using register indirect addressing modes with automatic pre-decrement and postincrement, the address registers X, Y, and Z are decremented and incremented. The 32 general purpose working registers, 64 I/O Registers, and the 1,024 bytes of internal data SRAM in the ATMEGA163 are all accessible through all these addressing modes. The Program and Data Addressing Modes The ATMEGA163 AVR Enhanced RISC microcontroller supports powerful and efficient addressing modes for access to the Program Memory (Flash) and Data Memory (SRAM, Register File, and I/O Memory). This section describes the different addressing modes supported by the AVR architecture. In the figures, OP means the operation code part of the instruction word. To simplify, not all figures show the exact location of the addressing bits. Figure 10. Direct Single Register Addressing Register Direct, Single Register Rd The operand is contained in register d (Rd). 12 ATMEGA163(L) 1142E-AVR-02/03 ATMEGA163(L) Register Direct, Two Registers Rd And Rr Figure 11. Direct Register Addressing, Two Registers Operands are contained in register r (Rr) and d (Rd). The result is stored in register d (Rd). I/O Direct Figure 12. I/O Direct Addressing Operand address is contained in 6 bits of the instruction word. n is the destination or source register address. Data Direct Figure 13. Direct Data Addressing Data Space 31 OP 16 LSBs 15 20 19 Rr/Rd 16 $0000 0 $045F A 16-bit Data Address is contained in the 16 LSBs of a two-word instruction. Rd/Rr specify the destination or source register. 13 1142E-AVR-02/03 Data Indirect with Displacement Figure 14. Data Indirect with Displacement Data Space $0000 15 Y OR Z - REGISTER 0 15 OP 10 n 65 a 0 $045F Operand address is the result of the Y- or Z-register contents added to the address contained in 6 bits of the instruction word. Data Indirect Figure 15. Data Indirect Addressing Data Space $0000 15 X, Y OR Z - REGISTER 0 $045F Operand address is the contents of the X-, Y-, or the Z-register. Data Indirect with Predecrement Figure 16. Data Indirect Addressing with Pre-decrement Data Space $0000 15 X, Y OR Z - REGISTER 0 -1 $045F The X-, Y-, or the Z-register is decremented before the operation. Operand address is the decremented contents of the X-, Y-, or the Z-register. 14 ATMEGA163(L) 1142E-AVR-02/03 ATMEGA163(L) Data Indirect with Postincrement Figure 17. Data Indirect Addressing with Post-increment Data Space $0000 15 X, Y OR Z - REGISTER 0 1 $045F The X-, Y-, or the Z-register is incremented after the operation. Operand address is the content of the X-, Y-, or the Z-register prior to incrementing. Constant Addressing Using The LPM and SPM Instructions Figure 18. Code Memory Constant Addressing $1FFF Constant byte address is specified by the Z-register contents. The 15 MSBs select word address (0 - 8K). For LPM, the LSB selects Low Byte if cleared (LSB = 0) or High Byte if set (LSB = 1). For SPM, the LSB should be cleared. Indirect Program Addressing, IJMP and ICALL Figure 19. Indirect Program Memory Addressing $1FFF Program execution continues at address contained by the Z-register (i.e., the PC is loaded with the contents of the Z-register). 15 1142E-AVR-02/03 Relative Program Addressing, RJMP and RCALL Figure 20. Relative Program Memory Addressing 1 $1FFF Program execution continues at address PC + k + 1. The relative address k is from -2,048 to 2,047. The EEPROM Data Memory The ATMEGA163 contains 512 bytes of data EEPROM memory. It is organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described on page 62 specifying the EEPROM Address Registers, the EEPROM Data Register, and the EEPROM Control Register. For the SPI data downloading, see page 154 for a detailed description. Memory Access Times and Instruction Execution Timing This section describes the general access timing concepts for instruction execution and internal memory access. The AVR CPU is driven by the System Clock O, directly generated from the main Oscillator for the chip. No internal clock division is used. Figure 21 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the fast-access Register File concept. This is the basic pipelining concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit. Figure 21. The Parallel Instruction Fetches and Instruction Executions T1 T2 T3 T4 System Clock O 1st Instruction Fetch 1st Instruction Execute 2nd Instruction Fetch 2nd Instruction Execute 3rd Instruction Fetch 3rd Instruction Execute 4th Instruction Fetch Figure 22 shows the internal timing concept for the Register File. In a single clock cycle an ALU operation using two register operands is executed, and the result is stored back to the destination register. 16 ATMEGA163(L) 1142E-AVR-02/03 ATMEGA163(L) Figure 22. Single Cycle ALU Operation T1 T2 T3 T4 System Clock O Total Execution Time Register Operands Fetch ALU Operation Execute Result Write Back The internal data SRAM access is performed in two System Clock cycles as described in Figure 23. Figure 23. On-chip Data SRAM Access Cycles T1 T2 T3 T4 System Clock O Address Data WR Data RD Prev. Address Address I/O Memory The I/O space definition of the ATMEGA163 is shown in the following table: Table 2. ATMEGA163 I/O Space (1) I/O Address (SRAM Address) $3F ($5F) $3E ($5E) $3D ($5D) $3B ($5B) $3A ($5A) $39 ($59) $38 ($58) $37 ($57) $36 ($56) $35 ($55) $34 ($54) $33 ($53) Name SREG SPH SPL GIMSK GIFR TIMSK TIFR SPMCR TWCR MCUCR MCUSR TCCR0 Function Status REGister Stack Pointer High Stack Pointer Low General Interrupt MaSK Register General Interrupt Flag Register Timer/Counter Interrupt MaSK Register Timer/Counter Interrupt Flag Register SPM Control Register Two-wire Serial Interface Control Register MCU general Control Register MCU general Status Register Timer/Counter0 Control Register 1142E-AVR-02/03 Read Write 17 Table 2. ATMEGA163 I/O Space (Continued) (1) I/O Address (SRAM Address) $32 ($52) $31 ($51) $30 ($50) $2F ($4F) $2E ($4E) $2D ($4D) $2C ($4C) $2B ($4B) $2A ($4A) $29 ($49) $28 ($48) $27 ($47) $26 ($46) $25 ($45) $24 ($44) $23 ($43) $22 ($42) $21 ($41) $20 ($40) $1F ($3F) $1E ($3E) $1D ($3D) $1C ($3C) $1B ($3B) $1A ($3A) $19 ($39) $18 ($38) $17 ($37) $16 ($36) $15 ($35) $14 ($34) $13 ($33) $12 ($32) $11 ($31) $10 ($30) Name TCNT0 OSCCAL SFIOR TCCR1A TCCR1B TCNT1H TCNT1L OCR1AH OCR1AL OCR1BH OCR1BL ICR1H ICR1L TCCR2 TCNT2 OCR2 ASSR WDTCR UBRRHI EEARH EEARL EEDR EECR PORTA DDRA PINA PORTB DDRB PINB PORTC DDRC PINC PORTD DDRD PIND Function Timer/Counter0 (8-bit) Oscillator Calibration Register Special Function I/O Register Timer/Counter1 Control Register A Timer/Counter1 Control Register B Timer/Counter1 High-byte Timer/Counter1 Low-byte Timer/Counter1 Output Compare Register A High-byte Timer/Counter1 Output Compare Register A Low-byte Timer/Counter1 Output Compare Register B High-byte Timer/Counter1 Output Compare Register B Low-byte T/C 1 Input Capture Register High-byte T/C 1 Input Capture Register Low-byte Timer/Counter2 Control Register Timer/Counter2 (8-bit) Timer/Counter2 Output Compare Register Asynchronous Mode Status Register Watchdog Timer Control Register UART Baud Rate Register High-byte EEPROM Address Register High-byte EEPROM Address Register Low-byte EEPROM Data Register EEPROM Control Register Data Register, Port A Data Direction Register, Port A Input Pins, Port A Data Register, Port B Data Direction Register, Port B Input Pins, Port B Data Register, Port C Data Direction Register, Port C Input Pins, Port C Data Register, Port D Data Direction Register, Port D Input Pins, Port D 18 ATMEGA163(L) 1142E-AVR-02/03 ATMEGA163(L) Table 2. ATMEGA163 I/O Space (Continued) (1) I/O Address (SRAM Address) $0F ($2F) $0E ($2E) $0D ($2D) $0C ($2C) $0B ($2B) $0A ($2A) $09 ($29) $08 ($28) $07 ($27) $06 ($26) $05 ($25) $04 ($24) $03 ($23) $02 ($22) $01 ($21) $00 ($20) Note: Name SPDR SPSR SPCR UDR UCSRA UCSRB UBRR ACSR ADMUX ADCSR ADCH ADCL TWDR TWAR TWSR TWBR Function SPI I/O Data Register SPI Status Register SPI Control Register UART I/O Data Register UART Control and Status Register A UART Control and Status Register B UART Baud Rate Register Analog Comparator Control and Status Register ADC Multiplexer Select Register ADC Control and Status Register ADC Data Register High ADC Data Register Low Two-wire Serial Interface Data Register Two-wire Serial Interface (Slave) Address Register Two-wire Serial Interface Status Register Two-wire Serial Interface Bit Rate Register 1. Reserved and unused locations are not shown in the table. All ATMEGA163 I/Os and peripherals are placed in the I/O space. The I/O locations are accessed by the IN and OUT instructions, transferring data between the 32 general purpose working registers and the I/O space. I/O Registers within the address range $00 $1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. Refer to the instruction set chapter for more details. When using the I/O specific commands IN and OUT, the I/O addresses $00 - $3F must be used. When addressing I/O Registers as SRAM, $20 must be added to these addresses. All I/O Register addresses throughout this document are shown with the SRAM address in parentheses. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. Some of the Status Flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate on all bits in the I/O Register, writing a one back into any Flag read as set, thus clearing the Flag. The CBI and SBI instructions work with registers $00 to $1F only. The I/O and Peripherals Control Registers are explained in the following sections. 19 1142E-AVR-02/03 The Status Register - SREG The AVR Status Register - SREG - at I/O space location $3F ($5F) is defined as: Bit $3F ($5F) Read/Write Initial Value 7 I R/W 0 6 T R/W 0 5 H R/W 0 4 S R/W 0 3 V R/W 0 2 N R/W 0 1 Z R/W 0 0 C R/W 0 SREG * Bit 7 - I: Global Interrupt Enable The Global Interrupt Enable bit must be set (one) for the interrupts to be enabled. The individual interrupt enable control is then performed in the Interrupt Mask Registers. If the Global Interrupt Enable Register is cleared (zero), none of the interrupts are enabled independent of the values of the Interrupt Mask Registers. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts. * Bit 6 - T: Bit Copy Storage The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source and destination for the operated bit. A bit from a register in the Register File can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the Register File by the BLD instruction. * Bit 5 - H: Half Carry Flag The Half Carry Flag H indicates a half carry in some arithmetic operations. See the Instruction Set Description for detailed information. * Bit 4 - S: Sign Bit, S = N V The S-bit is always an exclusive or between the Negative Flag N and the Two's Complement Overflow Flag V. See the Instruction Set Description for detailed information. * Bit 3 - V: Two's Complement Overflow Flag The Two's Complement Overflow Flag V supports two's complement arithmetics. See the Instruction Set Description for detailed information. * Bit 2 - N: Negative Flag The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the Instruction Set Description for detailed information. * Bit 1 - Z: Zero Flag The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the Instruction Set Description for detailed information. * Bit 0 - C: Carry Flag The Carry Flag C indicates a carry in an arithmetic or logic operation. See the Instruction Set Description for detailed information. Note that the Status Register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt routine. This must be handled by software. 20 ATMEGA163(L) 1142E-AVR-02/03 ATMEGA163(L) The Stack Pointer - SP The ATMEGA163 Stack Pointer is implemented as two 8-bit registers in the I/O space locations $3E ($5E) and $3D ($5D). As the ATMEGA163 data memory has $460 locations, 11 bits are used. Bit $3E ($5E) $3D ($5D) 15 - SP7 7 Read/Write R R/W Initial Value 0 0 14 - SP6 6 R R/W 0 0 13 - SP5 5 R R/W 0 0 12 - SP4 4 R R/W 0 0 11 - SP3 3 R R/W 0 0 10 SP10 SP2 2 R/W R/W 0 0 9 SP9 SP1 1 R/W R/W 0 0 8 SP8 SP0 0 R/W R/W 0 0 SPH SPL The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt Stacks are located. This Stack space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. The Stack Pointer must be set to point above $60. The Stack Pointer is decremented by one when data is pushed onto the Stack with the PUSH instruction, and it is decremented by two when the return address is pushed onto the Stack with subroutine call and interrupt. The Stack Pointer is incremented by one when data is popped from the Stack with the POP instruction, and it is incremented by two when data is popped from the Stack with return from subroutine RET or return from interrupt RETI. Reset and Interrupt Handling The ATMEGA163 provides 17 different interrupt sources. These interrupts and the separate Reset Vector, each have a separate Program Vector in the Program Memory space. All interrupts are assigned individual enable bits which must be set (one) together with the I-bit in the Status Register in order to enable the interrupt. The lowest addresses in the Program Memory space are automatically defined as the Reset and Interrupt Vectors. The complete list of vectors is shown in Table 3. The list also determines the priority levels of the different interrupts. The lower the address the higher is the priority level. RESET has the highest priority, and next is INT0 - the External Interrupt Request 0, etc. Table 3. Reset and Interrupt Vectors Vector No. 1 2 3 4 5 6 7 8 9 10 11 12 Program Address $000(1) $002 $004 $006 $008 $00A $00C $00E $010 $012 $014 $016 Source RESET INT0 INT1 TIMER2 COMP TIMER2 OVF TIMER1 CAPT TIMER1 COMPA TIMER1 COMPB TIMER1 OVF TIMER0 OVF SPI, STC UART, RXC Interrupt Definition External Pin, Power-on Reset, Brown-out Reset and Watchdog Reset External Interrupt Request 0 External Interrupt Request 1 Timer/Counter2 Compare Match Timer/Counter2 Overflow Timer/Counter1 Capture Event Timer/Counter1 Compare Match A Timer/Counter1 Compare Match B Timer/Counter1 Overflow Timer/Counter0 Overflow Serial Transfer Complete UART, Rx Complete 21 1142E-AVR-02/03 Table 3. Reset and Interrupt Vectors (Continued) Vector No. 13 14 15 16 17 18 Note: Program Address $018 $01A $01C $01E $020 $022 Source UART, UDRE UART, TXC ADC EE_RDY ANA_COMP TWI Interrupt Definition UART Data Register Empty UART, Tx Complete ADC Conversion Complete EEPROM Ready Analog Comparator Two-wire Serial Interface 1. When the BOOTRST Fuse is programmed, the device will jump to the Boot Loader address at reset, see "Boot Loader Support" on page 134. The most typical and general program setup for the Reset and Interrupt Vector Addresses in ATMEGA163 is: Address $000 $002 $004 $006 $008 $00a $00c $00e $010 $012 $014 $016 $018 $01a $01c $01e $020 $022 ; $024 $025 $026 $027 ... ... MAIN: ldi out ldi out ... r16,high(RAMEND) ; Main program start SPH,r16 SPL,r16 ; Set stack pointer to top of RAM r16,low(RAMEND) Labels Code jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp RESET EXT_INT0 EXT_INT1 TIM2_COMP TIM2_OVF TIM1_CAPT Comments ; Reset Handler ; IRQ0 Handler ; IRQ1 Handler ; Timer2 Compare Handler ; Timer2 Overflow Handler ; Timer1 Capture Handler TIM1_COMPA ; Timer1 Compare A Handler TIM1_COMPB ; Timer1 Compare B Handler TIM1_OVF TIM0_OVF SPI_STC UART_RXC UART_DRE UART_TXC ADC EE_RDY ANA_COMP TWI ; Timer1 Overflow Handler ; Timer0 Overflow Handler ; SPI Transfer Complete Handler ; UART RX Complete Handler ; UDR Empty Handler ; UART TX Complete Handler ; EEPROM Ready Handler ; Analog Comparator Handler ; Two-wire Serial Interface Interrupt Handler ; ADC Conversion Complete Interrupt Handler 22 ATMEGA163(L) 1142E-AVR-02/03 ATMEGA163(L) When the BOOTRST Fuse is programmed and the Boot section size set to 512 bytes, the most typical and general program setup for the Reset and Interrupt Vector Addresses in ATMEGA163 is: Address $002 ... $022 ; $024 $025 $026 $027 $028 ; .org $1f00 $1f00 jmp RESET ; Reset Handler MAIN: ldi out ldi out r16,high(RAMEND) ; Main program start SPH,r16 ; Set stack pointer to top of RAM ... Labels Code jmp ... jmp TWI ; Two-wire Serial Interface Interrupt Handler EXT_INT0 Comments ; IRQ0 Handler r16,low(RAMEND) SPL,r16 Reset Sources The ATMEGA163 has four sources of reset: * * * * Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (VPOT). External Reset. The MCU is reset when a low level is present on the RESET pin for more than 500 ns. Watchdog Reset. The MCU is reset when the Watchdog Timer period expires and the Watchdog is enabled. Brown-out Reset. The MCU is reset when the supply voltage VCC is below the Brown-out Reset threshold (VBOT). During Reset, all I/O Registers are set to their initial values, and the program starts execution from address $000 (unless the BOOTRST Fuse is programmed, as explained above). The instruction placed in this address location must be a JMP - absolute jump - instruction to the reset handling routine. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations. The circuit diagram in Figure 24 shows the Reset Logic. Table 4 and Table 5 define the timing and electrical parameters of the reset circuitry. 23 1142E-AVR-02/03 Figure 24. Reset Logic DATA BUS MCU Status Register (MCUSR) PORF BORF EXTRF WDRF VCC Power-on Reset Circuit BODEN BODLEVEL 100-500kW RESET SPIKE FILTER Brown-out Reset Circuit Internal Reset Reset Circuit Counter Reset Watchdog Timer On-chip RC Oscillator Clock Generator CK Delay Counters TIMEOUT CKSEL[3:0] Table 4. Reset Characteristics (VCC = 5.0V) Symbol VPOT Parameter Power-on Reset Threshold Voltage (rising) Power-on Reset Threshold Voltage (falling)(1) VRST VBOT Notes: RESET Pin Threshold Voltage Brown-out Reset Threshold Voltage (BODLEVEL = 1) (BODLEVEL = 0) Condition Min 1.0 0.4 - 2.4 3.5 Typ 1.4 0.6 - 2.7 4.0 Max 1.8 0.8 0.85 V CC 3.2 V 4.5 Units V V V 1. The Power-on Reset will not work unless the supply voltage has been below VPOT (falling). 24 ATMEGA163(L) 1142E-AVR-02/03 ATMEGA163(L) Table 5. Reset Delay Selections(1) Start-up Time, VCC = 2.7V, BODLEVEL Unprogrammed 4.2 ms + 6 CK 30 s + 6 CK(4) 67 ms + 6 CK 4.2 ms + 6 CK 30 s + 6 CK (4) CKSEL(2) 0000 0001 0010(6) 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Notes: 1. 2. 3. 4. 5. 6. Start-up Time, VCC = 4.0V, BODLEVEL Programmed 5.8 ms + 6 CK 10 s + 6 CK(5) 92 ms + 6 CK 5.8 ms + 6 CK 10 s + 6 CK (5) Recommended Usage(3) Ext. Clock, fast rising power Ext. Clock, BOD enabled Int. RC Oscillator, slowly rising power Int. RC Oscillator, fast rising power Int. RC Oscillator, BOD enabled Ext. RC Oscillator, slowly rising power Ext. RC Oscillator, fast rising power Ext. RC Oscillator, BOD enabled Ext. Low-frequency Crystal Ext. Low-frequency Crystal Crystal Oscillator, slowly rising power Crystal Oscillator, fast rising power Crystal Oscillator, BOD enabled Ceramic Resonator/Ext. Clock, slowly rising power Ceramic Resonator, fast rising power Ceramic Resonator, BOD enabled 67 ms + 6 CK 4.2 ms + 6 CK 30 s + 6 CK (4) 92 ms + 6 CK 5.8 ms + 6 CK 10 s + 6 CK (5) 67ms + 32K CK 67 ms + 1K CK 67 ms + 16K CK 4.2 ms + 16K CK 30 s + 16K CK (4) 92 ms + 32K CK 92 ms + 1K CK 92 ms + 16K CK 5.8 ms + 16K CK 10 s + 16K CK (5) 67 ms + 1K CK 4.2 ms + 1K CK 30 s + 1K CK (4) 92 ms + 1K CK 5.8 ms + 1K CK 10 s + 1K CK (5) On power-up, the start-up time is increased with typ. 0.6 ms. "1" means unprogrammed, "0" means programmed. For possible clock selections, see "Clock Options" on page 5. When BODEN is programmed, add 100 s. When BODEN is programmed, add 25 s. Default value. Table 5 shows the Start-up Times from Reset. When the CPU wakes up from Powerdown or Power-save, only the clock counting part of the start-up time is used. The Watchdog Oscillator is used for timing the real time part of the start-up time. The number of WDT Oscillator cycles used for each time-out is shown in Table 6. The frequency of the Watchdog Oscillator is voltage dependent as shown in the Electrical Characteristics section. The device is shipped with CKSEL = "0010" (Int. RC Oscillator, slowly rising power). 25 1142E-AVR-02/03 Table 6. Number of Watchdog Oscillator Cycles(1) BODLEVEL Unprogrammed Unprogrammed Unprogrammed Unprogrammed Programmed Programmed Programmed Programmed Note: VCC Condition 2.7V 2.7V 2.7V 2.7V 4.0V 4.0V 4.0V 4.0V Time-out 30 s 130 s 4.2 ms 67 ms 10 s 35 s 5.8 ms 92 ms Number of Cycles 8 32 1K 16K 8 32 4K 64K 1. The Bodlevel Fuse can be used to select start-up times even if the Brown-out Detection is disabled (BODEN Fuse unprogrammed). Power-on Reset A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level is defined in Table 4. The POR is activated whenever V CC is below the detection level. The POR circuit can be used to trigger the Start-up Reset, as well as to detect a failure in supply voltage. A Power-on Reset (POR) circuit ensures that the device is reset from Power-on. Reaching the Power-on Reset threshold voltage invokes a delay counter, which determines the delay, for which the device is kept in RESET after VCC rise. The Time-out Period of the delay counter can be defined by the user through the CKSEL Fuses. The different selections for the delay period are presented in Table 5. The RESET signal is activated again, without any delay, when the VCC decreases below detection level. Figure 25. MCU Start-up, RESET Tied to VCC. VCC VPOT RESET VRST TIME-OUT tTOUT INTERNAL RESET 26 ATMEGA163(L) 1142E-AVR-02/03 ATMEGA163(L) Figure 26. MCU Start-up, RESET Extended Externally VCC VPOT RESET VRST TIME-OUT tTOUT INTERNAL RESET External Reset An External Reset is generated by a low level on the RESET pin. Reset pulses longer than 500 ns will generate a Reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a Reset. When the applied signal reaches the Reset Threshold Voltage - VRST on its positive edge, the delay timer starts the MCU after the Time-out Period tTOUT has expired. Figure 27. External Reset During Operation Brown-out Detection ATMEGA163 has an On-chip Brown-out Detection (BOD) circuit for monitoring the VCC level during the operation. The BOD circuit can be enabled/disabled by the fuse BODEN. When the BOD is enabled (BODEN programmed), and VCC decreases to a value below the trigger level, the Brown-out Reset is immediately activated. When VCC increases above the trigger level, the Brown-out Reset is deactivated after a delay. The delay is defined by the user in the same way as the delay of POR signal, in Table 5. The trigger level for the BOD can be selected by the fuse BODLEVEL to be 2.7V (BODLEVEL unprogrammed), or 4.0V (BODLEVEL programmed). The trigger level has a hysteresis of 50 mV to ensure spike free Brown-out Detection. The BOD circuit will only detect a drop in VCC if the voltage stays below the trigger level for longer than 9 s for trigger level 4.0V, 21 s for trigger level 2.7V (typical values). 27 1142E-AVR-02/03 Figure 28. Brown-out Reset During Operation VCC VBOTVBOT+ RESET TIME-OUT tTOUT INTERNAL RESET The hysteresis on VBOT: VBOT+ = VBOT + 25 mV, VBOT- = VBOT - 25 mV Watchdog Reset When the Watchdog times out, it will generate a short reset pulse of 1 XTAL cycle duration. On the falling edge of this pulse, the delay timer starts counting the Time-out Period tTOUT. Refer to page 60 for details on operation of the Watchdog Timer. Figure 29. Watchdog Reset During Operation 1 CK Cycle MCU Status Register - MCUSR The MCU Status Register provides information on which reset source caused an MCU Reset. Bit $34 ($54) Read/Write Initial Value 7 - R 0 6 - R 0 5 - R 0 4 - R 0 3 WDRF R/W 2 BORF R/W 1 EXTRF R/W See Bit Description 0 PORF R/W MCUSR * Bits 7..4 - Res: Reserved Bits These bits are reserved bits in the ATMEGA163 and always read as zero. * Bit 3 - WDRF: Watchdog Reset Flag This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the Flag. 28 ATMEGA163(L) 1142E-AVR-02/03 ATMEGA163(L) * Bit 2 - BORF: Brown-out Reset Flag This bit is set if a Brown-out Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the Flag. * Bit 1 - EXTRF: External Reset Flag This bit is set if an External Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag. * Bit 0 - PORF: Power-on Reset Flag This bit is set if a Power-on Reset occurs. The bit is reset only by writing a logic zero to the flag. To make use of the Reset Flags to identify a reset condition, the user should read and then reset the MCUSR as early as possible in the program. If the register is cleared before another reset occurs, the source of the reset can be found by examining the Reset Flags. Internal Voltage Reference ATMEGA163 features an internal bandgap reference with a nominal voltage of 1.22V. This reference is used for Brown-out Detection, and it can be used as an input to the Analog Comparator and ADC. The 2.56V reference to the ADC is also generated from the internal bandgap reference. To save power, the reference is not always turned on. The reference is on during the following situations: 1. When the BOD is enabled (by programming the BODEN Fuse) 2. When the bandgap reference is connected to the Analog Comparator (by setting the ACBG bit in ACSR). 3. When the ADC is enabled. Thus, when the BOD is not enabled, after setting the ACBG bit, the user must always allow the reference to start up before the output from the Analog Comparator is used. The bandgap reference uses typically 10 A, and to reduce power consumption in Power-down mode, the user can avoid the three conditions above to ensure that the reference is turned off before entering Power-down mode. Interrupt Handling The ATMEGA163 has two 8-bit Interrupt Mask Control Registers: GIMSK - General Interrupt Mask Register and TIMSK - Timer/Counter Interrupt Mask Register. When an interrupt occurs, the Global Interrupt Enable I-bit is cleared (zero) and all interrupts are disabled. The user software must set (one) the I-bit to enable nested interrupts. The I-bit is set (one) when a Return from Interrupt instruction - RETI - is executed. When the Program Counter is vectored to the actual Interrupt Vector in order to execute the interrupt handling routine, hardware clears the corresponding flag that generated the interrupt. Some of the interrupt flags can also be cleared by writing a logic one to the flag bit position(s) to be cleared. If an interrupt condition occurs when the corresponding interrupt enable bit is cleared (zero), the Interrupt Flag will be set and remembered until the interrupt is enabled, or the flag is cleared by software. Voltage Reference Enable Signals and Start-up Time 29 1142E-AVR-02/03 If one or more interrupt conditions occur when the Global Interrupt Enable bit is cleared (zero), the corresponding interrupt flag(s) will be set and remembered until the Global Interrupt Enable bit is set (one), and will be executed by order of priority. Note that external level interrupt does not have a flag, and will only be remembered for as long as the interrupt condition is present. Note that the Status Register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt routine. This must be handled by software. Interrupt Response Time The interrupt execution response for all the enabled AVR interrupts is four clock cycles minimum. After four clock cycles the Program Vector address for the actual interrupt handling routine is executed. During this four clock cycle period, the Program Counter (13 bits) is pushed onto the Stack. The vector is normally a jump to the interrupt routine, and this jump takes three clock cycles. If an interrupt occurs during execution of a multicycle instruction, this instruction is completed before the interrupt is served. If an interrupt occurs when the MCU is in sleep mode, the interrupt execution response time is increased by four clock cycles. A return from an interrupt handling routine takes four clock cycles. During these four clock cycles, the Program Counter (two bytes) is popped back from the Stack, the Stack Pointer is incremented by two, and the I Flag in SREG is set. When AVR exits from an interrupt, it will always return to the main program and execute one more instruction before any pending interrupt is served. The General Interrupt Mask Register - GIMSK Bit $3B ($5B) Read/Write Initial Value 7 INT1 R/W 0 6 INT0 R/W 0 5 - R x 4 - R 0 3 - R 0 2 - R 0 1 - R 0 0 - R 0 GIMSK * Bit 7 - INT1: External Interrupt Request 1 Enable When the INT1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is activated. The Interrupt Sense Control1 bits 1/0 (ISC11 and ISC10) in the MCU general Control Register (MCUCR) define whether the external interrupt is activated on rising and/or falling edge of the INT1 pin or level sensed. Activity on the pin will cause an interrupt request even if INT1 is configured as an output. The corresponding interrupt of External Interrupt Request 1 is executed from program memory address $004. See also "External Interrupts". * Bit 6 - INT0: External Interrupt Request 0 Enable When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is activated. The Interrupt Sense Control0 bits 1/0 (ISC01 and ISC00) in the MCU General Control Register (MCUCR) define whether the external interrupt is activated on rising or falling edge of the INT0 pin or level sensed. Activity on the pin will cause an interrupt request even if INT0 is configured as an output. The corresponding interrupt of External Interrupt Request 0 is executed from Program Memory address $002. See also "External Interrupts." * Bits 5 - Res: Reserved Bits This bit is reserved in the ATMEGA163 and the read value is undefined. 30 ATMEGA163(L) 1142E-AVR-02/03 ATMEGA163(L) * Bits 4..0 - Res: Reserved Bits These bits are reserved bits in the ATMEGA163 and always read as zero. The General Interrupt Flag Register - GIFR Bit $3A ($5A) Read/Write Initial Value 7 INTF1 R/W 0 6 INTF0 R/W 0 5 - R 0 4 - R 0 3 - R 0 2 - R 0 1 - R 0 0 - R 0 GIFR * Bit 7 - INTF1: External Interrupt Flag1 When an edge on the INT1 pin triggers an interrupt request, the correspnding Interrupt Flag, INTF1, becomes set (one). If the I-bit in SREG and the corresponding Interrupt Enable bit, INT1 in GIMSK are set (one), the MCU will jump to the Interrupt Vector. The Flag is cleared when the interrupt routine is executed. Alternatively, the Flag can be cleared by writing a logical one to it. This Flag is always cleared when INT1 is configured as a level interrupt. * Bit 6 - INTF0: External Interrupt Flag0 When an event on the INT0 pin triggers an interrupt request, the corresponding Interrupt Flag, INTF0 becomes set (one). If the I-bit in SREG and the corresponding Interrupt Enable bit, INT0 in GIMSK are set (one), the MCU will jump to the Interrupt Vector. The Flag is cleared when the interrupt routine is executed. Alternatively, the Flag can be cleared by writing a logical one to it. This Flag is always cleared when INT0 is configured as a level interrupt. * Bits 5..0 - Res: Reserved Bits These bits are reserved bits in the ATMEGA163 and always read as zero. The Timer/Counter Interrupt Mask Register - TIMSK Bit $39 ($59) Read/Write Initial Value 7 OCIE2 R/W 0 6 TOIE2 R/W 0 5 TICIE1 R/W 0 4 OCIE1A R/W 0 3 OCIE1B R/W 0 2 TOIE1 R/W 0 1 - R 0 0 TOIE0 R/W 0 TIMSK * Bit 7 - OCIE2: Timer/Counter2 Output Compare Match Interrupt Enable When the OCIE2 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter2 Compare Match Interrupt is enabled. The corresponding interrupt (at vector $006) is executed if a Compare Match in Timer/Counter2 occurs, i.e., when the OCF2 bit is set in the Timer/Counter Interrupt Flag Register - TIFR. * Bit 6 - TOIE2: Timer/Counter2 Overflow Interrupt Enable When the TOIE2 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter2 Overflow Interrupt is enabled. The corresponding interrupt (at vector $008) is executed if an overflow in Timer/Counter2 occurs, i.e., when the TOV2 bit is set in the Timer/Counter Interrupt Flag Register - TIFR. * Bit 5 - TICIE1: Timer/Counter1 Input Capture Interrupt Enable When the TICIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Input Capture Event Interrupt is enabled. The corresponding interrupt 31 1142E-AVR-02/03 (at vector $00A) is executed if a capture triggering event occurs on PD6 (ICP), i.e., when the ICF1 bit is set in the Timer/Counter Interrupt Flag Register - TIFR. * Bit 4 - OCIE1A: Timer/Counter1 Output CompareA Match Interrupt Enable When the OCIE1A bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Compare A Match Interrupt is enabled. The corresponding interrupt (at vector $00C) is executed if a Compare A Match in Timer/Counter1 occurs, i.e., when the OCF1A bit is set in the Timer/Counter Interrupt Flag Register - TIFR. * Bit 3 - OCIE1B: Timer/Counter1 Output CompareB Match Interrupt Enable When the OCIE1B bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Compare B Match Interrupt is enabled. The corresponding interrupt (at vector $00E) is executed if a Compare B Match in Timer/Counter1 occurs, i.e., when the OCF1B bit is set in the Timer/Counter Interrupt Flag Register - TIFR. * Bit 2 - TOIE1: Timer/Counter1 Overflow Interrupt Enable When the TOIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Overflow Interrupt is enabled. The corresponding interrupt (at vector $010) is executed if an overflow in Timer/Counter1 occurs, i.e., when the TOV1 bit is set in the Timer/Counter Interrupt Flag Register - TIFR. * Bit 1 - Res: Reserved Bit This bit is a reserved bit in the ATMEGA163 and always reads as zero. * Bit 0 - TOIE0: Timer/Counter0 Overflow Interrupt Enable When the TOIE0 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter0 Overflow Interrupt is enabled. The corresponding interrupt (at vector $012) is executed if an overflow in Timer/Counter0 occurs, i.e., when the TOV0 bit is set in the Timer/Counter Interrupt Flag Register - TIFR. The Timer/Counter Interrupt Flag Register - TIFR Bit $38 ($58) Read/Write Initial Value 7 OCF2 R/W 0 6 TOV2 R/W 0 5 ICF1 R/W 0 4 OCF1A R/W 0 3 OCF1B R/W 0 2 TOV1 R/W 0 1 - R x 0 TOV0 R/W 0 TIFR * Bit 7 - OCF2: Output Compare Flag2 The OCF2 bit is set (one) when a Compare Match occurs between the Timer/Counter2 and the data in OCR2 - Output Compare Register2. OCF2 is cleared by hardware when executing the corresponding Interrupt Handling Vector. Alternatively, OCF2 is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE2 (Timer/Counter2 Compare Match Interrupt Enable), and the OCF2 are set (one), the Timer/Counter2 Compare Match Interrupt is executed. * Bit 6 - TOV2: Timer/Counter2 Overflow Flag The TOV2 bit is set (one) when an overflow occurs in Timer/Counter2. TOV2 is cleared by hardware when executing the corresponding inteRrupt Handling Vector. Alternatively, TOV2 is cleared by writing a logic one to the flag. When the SREG I-bit, and TOIE2 (Timer/Counter2 Overflow Interrupt Enable), and TOV2 are set (one), the 32 ATMEGA163(L) 1142E-AVR-02/03 ATMEGA163(L) Timer/Counter2 Overflow Interrupt is executed. In up/down PWM mode, this bit is set when Timer/Counter2 changes counting direction at $00. * Bit 5 - ICF1: Input Capture Flag1 The ICF1 bit is set (one) to Flag an Input Capture Event, indicating that the Timer/Counter1 value has been transferred to the Input Capture Register - ICR1. ICF1 is cleared by hardware when executing the corresponding Interrupt Handling Vector. Alternatively, ICF1 is cleared by writing a logic one to the flag. * Bit 4 - OCF1A: Output Compare Flag 1A The OCF1A bit is set (one) when a Compare Match occurs between the Timer/Counter1 and the data in OCR1A - Output Compare Register 1A. OCF1A is cleared by hardware when executing the corresponding Interrupt Handling Vector. Alternatively, OCF1A is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE1A (Timer/Counter1 Compare Match Interrupt A Enable), and the OCF1A are set (one), the Timer/Counter1A Compare Match Interrupt is executed. * Bit 3 - OCF1B: Output Compare Flag 1B The OCF1B bit is set (one) when a Compare Match occurs between the Timer/Counter1 and the data in OCR1B - Output Compare Register 1B. OCF1B is cleared by hardware when executing the corresponding Interrupt Handling Vector. Alternatively, OCF1B is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE1B (Timer/Counter1 Compare Match Interrupt B Enable), and the OCF1B are set (one), the Timer/Counter1B Compare Match Interrupt is executed. * Bit 2 - TOV1: Timer/Counter1 Overflow Flag The TOV1 is set (one) when an overflow occurs in Timer/Counter1. TOV1 is cleared by hardware when executing the corresponding Interrupt Handling Vector. Alternatively, TOV1 is cleared by writing a logic one to the flag. When the I-bit in SREG, and TOIE1 ( Time r /C o u n te r1 O ve r flo w In te r ru p t En a b le ), a n d TO V 1 a r e se t ( o ne ) , th e Timer/Counter1 Overflow Interrupt is executed. In up/down PWM mode, this bit is set when Timer/Counter1 changes counting direction at $0000. * Bit 1 - Res: Reserved Bit This bit is a reserved bit in the ATMEGA163 and the read value is undefined. * Bit 0 - TOV0: Timer/Counter0 Overflow Flag The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware when executing the corresponding Interrupt Handling Vector. Alternatively, TOV0 is cleared by writing a logic one to the flag. When the SREG I-bit, and TOIE0 ( Time r /C o u n te r0 O ve r flo w In te r ru p t En a b le ), a n d TO V 0 a r e se t ( o ne ) , th e Timer/Counter0 Overflow interrupt is executed. External Interrupts The external interrupts are triggered by the INT0 and INT1 pins. Observe that, if enabled, the interrupts will trigger even if the INT0/INT1 pins are configured as outputs. This feature provides a way of generating a software interrupt. The external interrupts can be triggered by a falling or rising edge or a low level. This is set up as indicated in the specification for the MCU Control Register - MCUCR. When the external interrupt is enabled and is configured as level triggered, the interrupt will trigger as long as the pin is held low. 33 1142E-AVR-02/03 MCU Control Register - MCUCR The MCU Control Register contains control bits for general MCU functions. Bit $35 ($55) Read/Write Initial Value 7 - R 0 6 SE R/W 0 5 SM1 R/W 0 4 SM0 R/W 0 3 ISC11 R/W 0 2 ISC10 R/W 0 1 ISC01 R/W 0 0 ISC00 R/W 0 MCUCR * Bit 7 - Res: Reserved Bit This bit is a reserved bit in the ATMEGA163 and always reads as zero. * Bit 6 - SE: Sleep Enable The SE bit must be set (one) to make the MCU enter the sleep mode when the SLEEP instruction is executed. To avoid the MCU entering the sleep mode unless it is the programmers purpose, it is recommended to set the Sleep Enable SE bit just before the execution of the SLEEP instruction. * Bits 5, 4 - SM1/SM0: Sleep Mode Select Bits 1 and 0 These bits select between the three available sleep modes as shown in Table 7. Table 7. Sleep Mode Select SM1 0 0 1 1 SM0 0 1 0 1 Sleep Mode Idle ADC Noise Reduction Power-down Power-save * Bits 3, 2 - ISC11, ISC10: Interrupt Sense Control 1 Bit 1 and Bit 0 The External Interrupt 1 is activated by the external pin INT1 if the SREG I-Flag and the corresponding interrupt mask in the GIMSK are set. The level and edges on the external INT1 pin that activate the interrupt are defined in Table 8. The value on the INT1 pin is sampled before detecting edges. If edge or toggle interrupt is selected, pulses that last longer than one clock period will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level interrupt is selected, the low level must be held until the completion of the currently executing instruction to generate an interrupt. Table 8. Interrupt 1 Sense Control ISC11 0 0 1 1 ISC10 0 1 0 1 Description The low level of INT1 generates an interrupt request. Any logical change on INT1 generates an interrupt request. The falling edge of INT1 generates an interrupt request. The rising edge of INT1 generates an interrupt request. 34 ATMEGA163(L) 1142E-AVR-02/03 ATMEGA163(L) * Bit 1, 0 - ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0 The External Interrupt 0 is activated by the external pin INT0 if the SREG I-Flag and the corresponding interrupt mask are set. The level and edges on the external INT0 pin that activate the interrupt are defined in Table 9. The value on the INT0 pin is sampled before detecting edges. If edge or toggle interrupt is selected, pulses that last longer than one clock period will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level interrupt is selected, the low level must be held until the completion of the currently executing instruction to generate an interrupt. Table 9. Interrupt 0 Sense Control ISC01 0 0 1 1 ISC00 0 1 0 1 Description The low level of INT0 generates an interrupt request. Any logical change on INT0 generates an interrupt request. The falling edge of INT0 generates an interrupt request. The rising edge of INT0 generates an interrupt request. Sleep Modes To enter any of the four sleep modes, the SE bit in MCUCR must be set (one) and a SLEEP instruction must be executed. The SM1 and SM0 bits in the MCUCR Register select which sleep mode (Idle, ADC Noise Reduction, Power-down, or Power-save) will be activated by the SLEEP instruction. See Table 7 for a summary. If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU wakes up. The MCU is then halted for four cycles, executes the interrupt routine, and resumes execution from the instruction following SLEEP. The contents of the Register File, SRAM, and I/O memory are unaltered when the device wakes up from sleep. If a Reset occurs during sleep mode, the MCU wakes up and executes from the Reset Vector. When the SM1/SM0 bits are set to 00, the SLEEP instruction makes the MCU enter Idle mode, stopping the CPU but allowing SPI, UART, Analog Comparator, ADC, Two-wire Serial Interface, Timer/Counters, Watchdog, and the interrupt system to continue operating (if enabled). This enables the MCU to wake up from external triggered interrupts as well as internal ones like the Timer Overflow and UART Receive Complete interrupts. If wake-up from the Analog Comparator interrupt is not required, the Analog Comparator can be powered down by setting the ACD bit in the Analog Comparator Control and Status Register - ACSR. This will reduce power consumption in Idle Mode. If the ADC is enabled, a conversion starts automatically when this mode is entered. When the SM1/SM0 bits are set to 01, the SLEEP instruction makes the MCU enter ADC Noise Reduction mode, stopping the CPU but allowing the ADC, the external interrupts, the Two-wire Serial Interface address watch, Timer/Counter2 and the Watchdog to continue operating (if enabled). This improves the noise environment for the ADC, enabling higher resolution measurements. If the ADC is enabled, a conversion starts automatically when this mode is entered. Apart from the ADC Conversion Complete interrupt, only an External Reset, a Watchdog Reset (if enabled), a Brown-out Reset, a Two-wire Serial Interface address match interrupt, or an external level interrupt can wake up the MCU from ADC Noise Reduction Mode. A Timer/Counter2 Output Compare or overflow event will wake up the MCU, but will not generate an interrupt unless Timer/Counter2 is clocked asynchronously. In future devices this is subject to change. It is recommended for future code compatibility to disable Timer/Counter2 interrupts during ADC Noise Reduction mode if the Timer/Counter2 is clocked synchronously. Idle Mode ADC Noise Reduction Mode 35 1142E-AVR-02/03 Power-down Mode When the SM1/SM0 bits are 10, the SLEEP instruction makes the MCU enter Powerdown mode. In this mode, the external Oscillator is stopped, while the external interrupts, the Two-wire Serial Interface address match, and the Watchdog continue operating (if enabled). Only an External Reset, a Watchdog Reset, a Brown-out Reset, a Two-wire Serial Interface address match interrupt, or an external level interrupt can wake up the MCU. Note that if a level triggered interrupt is used for wake-up from Power-down mode, the changed level must be held for some time to wake up the MCU. This makes the MCU less sensitive to noise. The changed level is sampled twice by the Watchdog Oscillator clock, and if the input has the required level during this time, the MCU will wake up. The period of the Watchdog Oscillator is 1 s (nominal) at 5.0V and 25C. The frequency of the Watchdog Oscillator is voltage dependent as shown in the Electrical Characteristics section. When waking up from Power-down mode, there is a delay from the wake-up condition occurs until the wake-up becomes effective. This allows the clock to restart and become stable after having been stopped. The wake-up period is defined by the same CKSEL Fuses that define the Reset Time-out period, as seen in Table 5 on page 25. Power-save Mode When the SM1/SM0 bits are 11, the SLEEP instruction forces the MCU into the Powersave mode. This mode is identical to Power-down, with one exception: If Timer/Counter2 is clocked asynchronously, i.e., the AS2 bit in ASSR is set, Timer/Counter2 will run during sleep. The device can wake up from either Timer Overf lo w o r O u tp u t C o m p a r e e v e n t fr o m Ti me r /C o u n te r2 i f t h e c o r r e s p o n d i n g Timer/Counter2 interrupt enable bits are set in TIMSK, and the global interrupt enable bit in SREG is set. If the asynchronous timer is NOT clocked asynchronously, Power-down mode is recommended instead of Power-save mode because the contents of the registers in the asynchronous timer should be considered undefined after wake-up in Power-save mode if AS2 is 0. 36 ATMEGA163(L) 1142E-AVR-02/03 ATMEGA163(L) Calibrated Internal RC Oscillator The calibrated internal Oscillator provides a fixed 1 MHz (nominal) clock at 5V and 25C. This clock may be used as the system clock. See the section "Clock Options" on page 5 for information on how to select this clock as the system clock. This Oscillator can be calibrated by writing the calibration byte to the OSCCAL Register. When this Oscillator is used as the chip clock, the Watchdog Oscillator will still be used for the Watchdog Timer and for the Reset Time-out. At 5V and 25oC, the pre-programmed calibration byte gives a frequency within 1% of the nominal frequency. For details on how to use the pre-programmed calibration value, see "Calibration Byte" on page 144. Oscillator Calibration Register - OSCCAL Bit $31 ($51) Read/Write Initial Value 7 CAL7 R/W 0 6 CAL6 R/W 0 5 CAL5 R/W 0 4 CAL4 R/W 0 3 CAL3 R/W 0 2 CAL2 R/W 0 1 CAL1 R/W 0 0 CAL0 R/W 0 * Bits 7..0 - CAL7..0: Oscillator Calibration Value Writing the calibration byte to this address will trim the internal Oscillator to remove process variations from the Oscillator frequency. When OSCCAL is zero, the lowest available frequency is chosen. Writing non-zero values to this register will increase the frequency of the internal Oscillator. Writing $FF to the register gives the highest available frequency. The calibrated Oscillator is used to time EEPROM and Flash access. If EEPROM or Flash is written, do not calibrate to more than 10% above the nominal frequency. Otherwise, the EEPROM or Flash write operation may fail. Note that the Oscillator is intended for calibration to 1.0MHz, thus tuning to other values is not guaranteed. Table 10. Internal RC Oscillator Frequency Range. OSCCAL Value $00 $7F $FF Min Frequency (MHz) 0.5 0.7 1.0 Max Frequency (MHz) 1.0 1.5 2.0 Special Function I/O Register - SFIOR Bit $30 ($50) Read/Write Initial Value 7 - R 0 6 - R 0 5 - R 0 4 - R 0 3 ACME R/W 0 2 PUD R/W 0 1 PSR2 R/W 0 0 PSR10 R/W 0 SFIOR * Bit 7..4 - Res: Reserved Bits These bits are reserved bits in the ATMEGA163 and always read as zero. * Bit 3 - ACME: Analog Comparator Multiplexer Enable When this bit is set (one) and the ADC is switched off (ADEN in ADCSR is zero), the ADC multiplexer selects the negative input to the Analog Comparator. When this bit is cleared (zero), AIN1 is applied to the negative input of the Analog Comparator. For a detailed description of this bit, see "Analog Comparator Multiplexed Input" on page 104. 37 1142E-AVR-02/03 * Bit 2 - PUD: Pull-up Disable When this bit is set (one), all pull-ups on all ports are disabled. If the bit is cleared (zero), the pull-ups can be individually enabled as described in the chapter "I/O Ports" on page 115. * Bit 1 - PSR2: Prescaler Reset Timer/Counter2 When this bit is set (one) the Timer/Counter2 Prescaler will be reset. The bit will be cleared by hardware after the operation is performed. Writing a zero to this bit will have no effect. This bit will always be read as zero if Timer/Counter2 is clocked by the internal CPU clock. If this bit is written when Timer/Counter2 is operating in asynchronous mode. The bit will remain one until the prescaler has been reset. See "Asynchronous Operation of Timer/Counter2" on page 58 for a detailed description of asynchronous operation. * Bit 0 - PSR10: Prescaler Reset Timer/Counter1 and Timer/Counter0 When this bit is set (one) the Timer/Counter1 and Timer/Counter0 Prescaler will be reset. The bit will be cleared by hardware after the operation is performed. Writing a zero to this bit will have no effect. Note that Timer/Counter1 and Timer/Counter0 share the same prescaler and a reset of this prescaler will affect both timers. This bit will always be read as zero. 38 ATMEGA163(L) 1142E-AVR-02/03 ATMEGA163(L) Timer/Counters The ATMEGA163 provides three general purpose Timer/Counters - two 8-bit T/Cs and one 16-bit T/C. Timer/Counter2 can optionally be asynchronously clocked from an external Oscillator. This Oscillator is optimized for use with a 32.768 kHz watch crystal, enabling use of Timer/Counter2 as a Real Time Clock (RTC). Timer/Counter0 and Timer/Counter1 have individual prescaling selection from the same 10-bit prescaler. Timer/Counter2 has its own prescaler. Both these prescalers can be reset by setting the corresponding control bits in the Special Functions I/O Register (SFIOR). These Timer/Counters can either be used as a timer with an internal clock time-base or as a counter with an external pin connection which triggers the counting. Figure 30. Prescaler for Timer/Counter0 and Timer/Counter1 Clear Timer/Counter Prescalers PSR10 TCK1 TCK0 For Timer/Counter0 and Timer/Counter1, the four different prescaled selections are: CK/8, CK/64, CK/256, and CK/1024, where CK is the Oscillator clock. For the two Timer/Counter0 and Timer/Counter1, CK, external source, and stop can also be selected as clock sources. Setting the PSR10 bit in SFIOR resets the prescaler. This allows the user to operate with a predictable prescaler. Note that Timer/Counter1 and Timer/Counter0 share the same prescaler and a Prescaler Reset will affect both Timer/Counters. 39 1142E-AVR-02/03 Figure 31. Prescaler for Timer/Counter2 CK TOSC1 PCK2 Clear PCK2/8 10-BIT T/C PRESCALER PCK2/1024 PCK2/128 PCK2/256 PCK2/32 PCK2/64 AS2 PSR2 0 CS20 CS21 CS22 TIMER/COUNTER2 CLOCK SOURCE TCK2 The clock source for Timer/Counter2 is named PCK2. PCK2 is by default connected to the main system clock CK. By setting the AS2 bit in ASSR, Timer/Counter2 is asynchronously clocked from the PC6(TOSC1) pin. This enables use of Timer/Counter2 as a Real Time Clock (RTC). When AS2 is set, pins PC6(TOSC1) and PC7(TOSC2) are disconnected from Port C. A crystal can then be connected between the PC6(TOSC1) and PC7(TOSC2) pins to serve as an independent clock source for Timer/Counter2. The Oscillator is optimized for use with a 32.768 kHz crystal. Applying an external clock source to TOSC1 is not recommended. Setting the PSR2 bit in SFIOR resets the prescaler. This allows the user to operate with a predictable prescaler. 8-bit Timer/Counter0 Figure 32 shows the block diagram for Timer/Counter0. The 8-bit Timer/Counter0 can select clock source from CK, prescaled CK, or an external pin. In addition it can be stopped as described in "Timer/Counter0 Control Register - TCCR0" on page 41. The overflow Status Flag is found in "The Timer/Counter Interrupt Flag Register - TIFR" on page 32. Control signals are found in the Timer/Counter0 Control Register - TCCR0. The interrupt enable/disable settings for Timer/Counter0 are found in "The Timer/Counter Interrupt Mask Register - TIMSK" on page 31. When Timer/Counter0 is externally clocked, the external signal is synchronized with the Oscillator frequency of the CPU. To assure proper sampling of the external clock, the minimum time between two external clock transitions must be at least one internal CPU clock period. The external clock signal is sampled on the rising edge of the internal CPU clock. The 8-bit Timer/Counter0 features both a high resolution and a high accuracy usage with the lower prescaling opportunities. Similarly, the high prescaling opportunities make the Timer/Counter0 useful for lower speed functions or exact timing functions with infrequent actions. 40 ATMEGA163(L) 1142E-AVR-02/03 ATMEGA163(L) Figure 32. Timer/Counter0 Block Diagram T/C0 OVERFLOW IRQ 8-BIT DATA BUS OCIE2 TICIE1 OCIE1B OCIE1A TIMER INT. MASK REGISTER (TIMSK) OCF2 TOIE2 TOIE1 TOIE0 TIMER INT. FLAG REGISTER (TIFR) TOV2 OCF1B OCF1A TOV1 TOV0 ICF1 T/C0 CONTROL REGISTER (TCCR0) CS02 CS01 CS00 7 TIMER/COUNTER0 (TCNT0) 0 T/C CLK SOURCE CONTROL LOGIC CK Timer/Counter0 Control Register - TCCR0 Bit $33 ($53) Read/Write Initial Value 7 - R 0 6 - R 0 5 - R 0 4 - R 0 3 - R 0 2 CS02 R/W 0 1 CS01 R/W 0 0 CS00 R/W 0 TCCR0 * Bits 7..3 - Res: Reserved Bits These bits are reserved bits in the ATMEGA163 and always read as zero. * Bits 2..0 - CS02, CS01, CS00: Clock Select0, Bit 2, 1, and 0 The Clock Select0 bits 2,1, and 0 define the prescaling source of Timer0. Table 11. Clock0 Prescale Select CS02 0 0 0 0 1 1 1 1 CS01 0 0 1 1 0 0 1 1 CS00 0 1 0 1 0 1 0 1 Description Stop, Timer/Counter0 is stopped. CK CK/8 CK/64 CK/256 CK/1024 External Pin T0, falling edge External Pin T0, rising edge The Stop condition provides a Timer Enable/Disable function. The prescaled CK modes are scaled directly from the CK Oscillator clock. If the external pin modes are used for Timer/Counter0, transitions on PB0/(T0) will clock the counter even if the pin is configured as an output. This feature can give the user SW control of the counting. 41 1142E-AVR-02/03 Timer/Counter 0 - TCNT0 Bit $34 ($54) Read/Write Initial Value 7 MSB R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 6 5 4 3 2 1 0 LSB R/W 0 TCNT0 The Timer/Counter0 is implemented as an up-counter with read and write access. If the Timer/Counter0 is written and a clock source is present, the Timer/Counter0 continues counting in the clock cycle following the write operation. 16-bit Timer/Counter1 Figure 33 shows the block diagram for Timer/Counter1. Figure 33. Timer/Counter1 Block Diagram T/C1 OVERFLOW IRQ T/C1 COMPARE MATCH A IRQ T/C1 COMPARE T/C1 INPUT MATCH B IRQ CAPTURE IRQ 8-BIT DATA BUS OCIE1B OCIE1A OCF1B OCF1A OCIE2 TICIE1 TOIE2 TOIE1 TOIE0 OCF2 TOV2 TIMER INT. MASK REGISTER (TIMSK) TIMER INT. FLAG REGISTER (TIFR) OCF1B OCF1A ICF1 TOV1 TOV1 ICF1 TOV0 T/C1 CONTROL REGISTER A (TCCR1A) FOC1B PWM11 COM1A1 COM1B1 PWM10 COM1A0 COM1B0 FOC1A T/C1 CONTROL REGISTER B (TCCR1B) ICNC1 CTC1 CS12 ICES1 CS10 CS11 15 87 T/C1 INPUT CAPTURE REGISTER (ICR1) 0 CONTROL LOGIC T1 CK CAPTURE TRIGGER 15 87 TIMER/COUNTER1 (TCNT1) 0 T/C CLEAR T/C CLOCK SOURCE UP/DOWN 15 8 7 0 15 8 7 0 16 BIT COMPARATOR 16 BIT COMPARATOR 15 8 7 0 15 8 7 0 TIMER/COUNTER1 OUTPUT COMPARE REGISTER A TIMER/COUNTER1 OUTPUT COMPARE REGISTER B The 16-bit Timer/Counter1 can select clock source from CK, prescaled CK, or an external pin. In addition it can be stopped as described in section "Timer/Counter1 Control Register B - TCCR1B" on page 45. The different Status Flags (Overflow, Compare Match, and Capture Event) are found in the Timer/Counter Interrupt Flag Register - TIFR. Control signals are found in the Timer/Counter1 Control Registers - TCCR1A and TCCR1B. The interrupt enable/disable settings for Timer/Counter1 are found in the Timer/Counter Interrupt Mask Register - TIMSK. When Timer/Counter1 is externally clocked, the external signal is synchronized with the Oscillator frequency of the CPU. To assure proper sampling of the external clock, the minimum time between two external clock transitions must be at least one internal CPU 42 ATMEGA163(L) 1142E-AVR-02/03 ATMEGA163(L) clock period. The external clock signal is sampled on the rising edge of the internal CPU clock. The 16-bit Timer/Counter1 features both a high resolution and a high accuracy usage with the lower prescaling opportunities. Similarly, the high prescaling opportunities makes the Timer/Counter1 useful for lower speed functions or exact timing functions with infrequent actions. The Timer/Counter1 supports two Output Compare functions using the Output Compare Register 1 A and B (OCR1A and OCR1B) as the data sources to be compared to the Timer/Counter1 contents. The Output Compare functions includes optional clearing of the counter on Compare A Match, and actions on the Output Compare pins on both compare matches. Timer/Counter1 can also be used as an 8-, 9-, or 10-bit Pulse Width Modulator (PWM). In this mode the counter and the OCR1A/OCR1B Registers serve as a dual glitch-free stand-alone PWM with centered pulses. Alternatively, the Timer/Counter1 can be configured to operate at twice the speed in PWM mode, but without centered pulses. Refer to page 48 for a detailed description of this function. The Input Capture function of Timer/Counter1 provides a capture of the Timer/Counter1 contents to the Input Capture Register - ICR1, triggered by an external event on the Input Capture Pin - ICP. The actual capture event settings are defined by the Timer/Counter1 Control Register - TCCR1B. In addition, the Analog Comparator can be set to trigger the Input Capture. Refer to the section, "The Analog Comparator" on page 102, for details on this. The ICP pin logic is shown in Figure 34. Figure 34. ICP Pin Schematic Diagram If the noise canceler function is enabled, the actual trigger condition for the capture event is monitored over four samples, and all four must be equal to activate the Capture Flag. 43 1142E-AVR-02/03 Timer/Counter1 Control Register A - TCCR1A Bit $2F ($4F) Read/Write Initial Value 7 COM1A1 R/W 0 6 COM1A0 R/W 0 5 COM1B1 R/W 0 4 COM1B0 R/W 0 3 FOC1A R/W 0 2 FOC1B R/W 0 1 PWM11 R/W 0 0 PWM10 R/W 0 TCCR1A * Bits 7, 6 - COM1A1, COM1A0: Compare Output Mode1A, Bits 1, and 0 The COM1A1 and COM1A0 control bits determine any output pin action following a Compare Match in Timer/Counter1. Any output pin actions affect pin OC1A - Output Compare A. This is an alternative function to an I/O Port, and the corresponding direction control bit must be set (one) to control an output pin. The control configuration is shown in Table 10. * Bits 5, 4 - COM1B1, COM1B0: Compare Output Mode1B, Bits 1, and 0 The COM1B1 and COM1B0 control bits determine any output pin action following a Compare Match in Timer/Counter1. Any output pin actions affect pin OC1B - Output Compare B. This is an alternative function to an I/O port, and the corresponding direction control bit must be set (one) to control an output pin. The control configuration is shown in Table 10. Table 12. Compare 1 Mode Select(1) COM1X1 0 0 1 1 Note: COM1X0 0 1 0 1 1. X = A or B. Description Timer/Counter1 disconnected from output pin OC1X Toggle the OC1X output line. Clear the OC1X output line (to zero). Set the OC1X output line (to one). In PWM mode, these bits have a different function. Refer to Table 14 for a detailed description. * Bit 3 - FOC1A: Force Output Compare1A Writing a logical one to this bit, forces a change in the Compare Match Output pin PD5 according to the values already set in COM1A1 and COM1A0. If the COM1A1 and COM1A0 bits are written in the same cycle as FOC1A, the new settings will not take effect until next Compare Match or Forced Compare Match occurs. The Force Output Compare bit can be used to change the output pin without waiting for a Compare Match in the Timer. The automatic action programmed in COM1A1 and COM1A0 happens as if a Compare Match had occurred, but no interrupt is generated and it will not clear the timer even if CTC1 in TCCR1B is set. The corresponding I/O pin must be set as an output pin for the FOC1A bit to have effect on the pin. The FOC1A bit will always be read as zero. The setting of the FOC1A bit has no effect in PWM mode. * Bit 2 - FOC1B: Force Output Compare1B Writing a logical one to this bit, forces a change in the Compare Match Output pin PD4 according to the values already set in COM1B1 and COM1B0. If the COM1B1 and COM1B0 bits are written in the same cycle as FOC1B, the new settings will not take effect until next Compare Match or Forced Compare Match occurs. The Force Output Compare bit can be used to change the output pin without waiting for a Compare Match 44 ATMEGA163(L) 1142E-AVR-02/03 ATMEGA163(L) in the Timer. The automatic action programmed in COM1B1 and COM1B0 happens as if a Compare Match had occurred, but no interrupt is generated. The corresponding I/O pin must be set as an output pin for the FOC1B bit to have effect on the pin. The FOC1B bit will always be read as zero. The setting of the FOC1B bit has no effect in PWM mode. * Bits 1..0 - PWM11, PWM10: Pulse Width Modulator Select Bits These bits select PWM operation of Timer/Counter1 as specified in Table 11. This mode is described on page 48. Table 13. PWM Mode Select PWM11 0 0 1 1 PWM10 0 1 0 1 Description PWM operation of Timer/Counter1 is disabled Timer/Counter1 is an 8-bit PWM Timer/Counter1 is a 9-bit PWM Timer/Counter1 is a 10-bit PWM Timer/Counter1 Control Register B - TCCR1B Bit $2E ($4E) Read/Write Initial Value 7 ICNC1 R/W 0 6 ICES1 R/W 0 5 - R 0 4 - R 0 3 CTC1 R/W 0 2 CS12 R/W 0 1 CS11 R/W 0 0 CS10 R/W 0 TCCR1B * Bit 7 - ICNC1: Input Capture1 Noise Canceler (4 CKs) When the ICNC1 bit is cleared (zero), the Input Capture trigger noise canceler function is disabled. The Input Capture is triggered at the first rising/falling edge sampled on the ICP - Input Capture Pin - as specified. When the ICNC1 bit is set (one), four successive samples are measures on the ICP - Input Capture Pin, and all samples must be high/low according to the Input Capture trigger specification in the ICES1 bit. The actual sampling frequency is XTAL clock frequency. * Bit 6 - ICES1: Input Capture1 Edge Select While the ICES1 bit is cleared (zero), the Timer/Counter1 contents are transferred to the Input Capture Register - ICR1 - on the falling edge of the Input Capture Pin - ICP. While the ICES1 bit is set (one), the Timer/Counter1 contents are transferred to the Input Capture Register - ICR1 - on the rising edge of the Input Capture Pin - ICP. * Bits 5, 4 - Res: Reserved Bits These bits are reserved bits in the ATMEGA163 and always read as zero. * Bit 3 - CTC1: Clear Timer/Counter1 on Compare Match When the CTC1 control bit is set (one), the Timer/Counter1 is Reset to $0000 in the clock cycle after a Compare A Match. If the CTC1 control bit is cleared, Timer/Counter1 continues counting and is unaffected by a Compare Match. When a prescaling of 1 is used, and the Compare A Register is set to C, the timer will count as follows if CTC1 is set: ... | C-1 | C | 0 | 1 |... 45 1142E-AVR-02/03 When the prescaler is set to divide by eight, the Timer will count like this: ... | C-1, C-1, C-1, C-1, C-1, C-1, C-1, C-1 | C, C, C, C, C, C, C, C | 0, 0, 0, 0, 0, 0, 0, 0 |1,1,1,1,1,1,1,1|... In PWM mode, this bit has a different function. If the CTC1 bit is cleared in PWM mode, the Timer/Counter1 acts as an up/down counter. If the CTC1 bit is set (one), the Timer/Counter wraps when it reaches the TOP value. Refer to page 48 for a detailed description. * Bits 2..0 - CS12, CS11, CS10: Clock Select1, Bit 2, 1, and 0 The Clock Select1 bits 2, 1, and 0 define the prescaling source of Timer/Counter1. Table 14. Clock 1 Prescale Select CS12 0 0 0 0 1 1 1 1 CS11 0 0 1 1 0 0 1 1 CS10 0 1 0 1 0 1 0 1 Description Stop, the Timer/Counter1 is stopped. CK CK/8 CK/64 CK/256 CK/1024 External Pin T1, falling edge External Pin T1, rising edge The Stop condition provides a Timer Enable/Disable function. The prescaled modes are scaled directly from the CK Oscillator clock. If the external pin modes are used for Timer/Counter1, transitions on PB1/(T1) will clock the counter even if the pin is configured as an output. This feature can give the user SW control of the counting. Timer/Counter1 - TCNT1H and TCNT1L Bit $2D ($4D) $2C ($4C) 15 MSB 14 13 12 11 10 9 8 TCNT1H LSB TCNT1L 7 Read/Write R/W R/W Initial Value 0 0 6 R/W R/W 0 0 5 R/W R/W 0 0 4 R/W R/W 0 0 3 R/W R/W 0 0 2 R/W R/W 0 0 1 R/W R/W 0 0 0 R/W R/W 0 0 This 16-bit register contains the prescaled value of the 16-bit Timer/Counter1. To ensure that both the high and low bytes are read and written simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary register (TEMP). This temporary register is also used when accessing OCR1A, OCR1B, and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program and interrupt routines. 46 ATMEGA163(L) 1142E-AVR-02/03 ATMEGA163(L) TCNT1 Timer/Counter1 Write When the CPU writes to the high byte TCNT1H, the written data is placed in the TEMP Register. Next, when the CPU writes the low byte TCNT1L, this byte of data is combined with the byte data in the TEMP Register, and all 16 bits are written to the TCNT1 Timer/Counter1 Register simultaneously. Consequently, the high byte TCNT1H must be accessed first for a full 16-bit register write operation. When the CPU reads the low byte TCNT1L, the data of the Low Byte TCNT1L is sent to the CPU and the data of the High Byte TCNT1H is placed in the TEMP Register. When the CPU reads the data in the High Byte TCNT1H, the CPU receives the data in the TEMP Register. Consequently, the Low Byte TCNT1L must be accessed first for a full 16-bit register read operation. The Timer/Counter1 is realized as an up or up/down (in PWM mode) counter with read and write access. If Timer/Counter1 is written to and a clock source is selected, the Timer/Counter1 continues counting in the timer clock cycle after it is preset with the written value. Timer/Counter1 Output Compare Register - OCR1AH and OCR1AL TCNT1 Timer/Counter1 Read Bit $2B ($4B) $2A ($4A) 15 MSB 14 13 12 11 10 9 8 OCR1AH LSB OCR1AL 7 Read/Write R/W R/W Initial Value 0 0 6 R/W R/W 0 0 5 R/W R/W 0 0 4 R/W R/W 0 0 3 R/W R/W 0 0 2 R/W R/W 0 0 1 R/W R/W 0 0 0 R/W R/W 0 0 Timer/Counter1 Output Compare Register - OCR1BH and OCR1BL Bit $29 ($49) $28 ($48) 15 MSB 14 13 12 11 10 9 8 OCR1BH LSB OCR1BL 7 Read/Write R/W R/W Initial Value 0 0 6 R/W R/W 0 0 5 R/W R/W 0 0 4 R/W R/W 0 0 3 R/W R/W 0 0 2 R/W R/W 0 0 1 R/W R/W 0 0 0 R/W R/W 0 0 The Output Compare Registers are 16-bit read/write registers. The Timer/Counter1 Output Compare Registers contain the data to be continuously compared with Timer/Counter1. Actions on compare matches are specified in the Timer/Counter1 Control and Status Register. A software write to the Timer/Counter Register blocks compare matches in the next Timer/Counter clock cycle. This prevents immediate interrupts when initializing the Timer/Counter. A Compare Match will set the compare interrupt flag in the CPU clock cycle following the compare event. Since the Output Compare Registers - OCR1A and OCR1B - are 16-bit registers, a temporary register TEMP is used when OCR1A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR1AH or OCR1BH, the data is temporarily stored in the TEMP Register. When the CPU writes the Low Byte, OCR1AL or OCR1BL, the TEMP Register is simultaneously written to OCR1AH or OCR1BH. Consequently, the high byte OCR1AH or OCR1BH must be written first for a full 16-bit register write operation. 47 1142E-AVR-02/03 The TEMP Register is also used when accessing TCNT1 and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program and interrupt routines. Timer/Counter1 Input Capture Register - ICR1H and ICR1L Bit $27 ($47) $26 ($46) 15 MSB 14 13 12 11 10 9 8 ICR1H LSB ICR1L 7 Read/Write R R Initial Value 0 0 6 R R 0 0 5 R R 0 0 4 R R 0 0 3 R R 0 0 2 R R 0 0 1 R R 0 0 0 R R 0 0 The Input Capture Register is a 16-bit read-only register. When the rising or falling edge (according to the input capture edge setting - ICES1) of the signal at the Input Capture Pin - ICP - is detected, the current value of the Timer/Counter1 Register - TCNT1 - is transferred to the Input Capture Register - ICR1. At the same time, the Input Capture Flag - ICF1 - is set (one). Since the Input Capture Register - ICR1 - is a 16-bit register, a temporary register TEMP is used when ICR1 is read to ensure that both bytes are read simultaneously. When the CPU reads the Low Byte ICR1L, the data is sent to the CPU and the data of the High Byte ICR1H is placed in the TEMP Register. When the CPU reads the data in the High Byte ICR1H, the CPU receives the data in the TEMP Register. Consequently, the Low Byte ICR1L must be accessed first for a full 16-bit register read operation. The TEMP Register is also used when accessing TCNT1, OCR1A, and OCR1B. If the main program and also interrupt routines accesses registers using TEMP, interrupts must be disabled during access from the main program and interrupt routines. Timer/Counter1 in PWM Mode When the PWM mode is selected, Timer/Counter1 and the Output Compare Register1A - OCR1A and the Output Compare Register1B - OCR1B, form a dual 8,- 9-, or 10-bit, free-running, glitch-free, and phase correct PWM with outputs on the PD5 (OC1A) and PD4(OC1B) pins. In this mode, the Timer/Counter1 acts as an up/down counter, counting up from $0000 to TOP (see Table 16), where it turns and counts down again to zero before the cycle is repeated. When the counter value matches the contents of the 8, 9, or 10 least significant bits (depending on resolution) of OCR1A or OCR1B, the PD5(OC1A)/PD4(OC1B) pins are set or cleared according to the settings of the COM1A1/COM1A0 or COM1B1/COM1B0 bits in the Timer/Counter1 Control Register TCCR1A. Refer to Table 12 on page 44 for details. Alternatively, the Timer/Counter1 can be configured to a PWM that operates at twice the speed as in the mode described above. Then the Timer/Counter1 and the Output Compare Register1A - OCR1A and the Output Compare Register1B - OCR1B, form a dual 8-, 9-, or 10-bit, free-running and glitch-free PWM with outputs on the PD5(OC1A) and PD4(OC1B) pins. 48 ATMEGA163(L) 1142E-AVR-02/03 ATMEGA163(L) Table 15. Timer TOP Values and PWM Frequency CTC1 0 0 0 1 1 1 PWM11 0 1 1 0 1 1 PWM10 1 0 1 1 0 1 PWM Resolution 8-bit 9-bit 10-bit 8-bit 9-bit 10-bit Timer TOP Value $00FF (255) $01FF (511) $03FF(1023) $00FF (255) $01FF (511) $03FF(1023) Frequency fTCK1/510 fTCK1/1022 fTCK1/2046 fTCK1/256 fTCK1/512 fTCK1/1024 As shown in Table 15, the PWM operates at either 8, 9, or 10 bits resolution. Note the unused bits in OCR1A, OCR1B, and TCNT1 will automatically be written to zero by hardware. For example, bit 9 to 15 will be set to zero in OCR1A, OCR1B, and TCNT1 if the 9-bit PWM resolution is selected. This makes it possible for the user to perform readmodify-write operations in any of the three resolution modes and the unused bits will be treated as don't care. Table 16. Timer TOP Values and PWM Frequency PWM Resolution 8-bit 9-bit 10-bit Timer TOP Value $00FF (255) $01FF (511) $03FF(1023) Frequency fTC1/510 fTC1/1022 fTC1/2046 Table 17. Compare1 Mode Select in PWM Mode(1) CTC1 0 0 0 0 1 1 1 1 Note: COM1X 1 0 0 1 1 0 0 1 1 1. X = A or B COM1X 0 0 1 0 1 0 1 0 1 Effect on OCX1 Not connected Not connected Cleared on Compare Match, up-counting. Set on Compare Match, down-counting (non-inverted PWM). Cleared on Compare Match, down-counting. Set on Compare Match, up-counting (inverted PWM). Not connected Not connected Cleared on Compare Match, set on overflow. Set on Compare Match, cleared on overflow. Note that in the PWM mode, the 8, 9, or 10 least significant OCR1A/OCR1B bits (depending on resolution), when written, are transferred to a temporary location. They are latched when Timer/Counter1 reaches the value TOP. This prevents the occurrence of odd-length PWM pulses (glitches) in the event of an unsynchronized OCR1A/OCR1B write. See Figure 35 and Figure 36 for an example in each mode. 49 1142E-AVR-02/03 Figure 35. Effects of Unsynchronized OCR1 Latching. PWM Output OC1x Synchronized OC1x Latch PWM Output OC1x Unsynchronized OC1x Latch Note: x = A or B Figure 36. Effects of Unsynchronized OCR1 Latching in Overflow Mode. PWM Output OC1x Synchronized OC1x Latch PWM Output OC1x Unsynchronized OC1x Latch Note: X = A or B During the time between the write and the latch operation, a read from OCR1A or OCR1B will read the contents of the temporary location. This means that the most recently written value always will read out of OCR1A/B. When the OCR1X contains $0000 or TOP, and the up/down PWM mode is selected, the output OC1A/OC1B is updated to low or high on the next Compare Match according to the settings of COM1A1/COM1A0 or COM1B1/COM1B0. This is shown in Table 18. In overflow PWM mode, the output OC1A/OC1B is held low or high only when the Output Compare Register contains TOP. Table 18. PWM Outputs OCR1X = $0000 or TOP(1) COM1X1 1 1 1 1 Note: 1. X = A or B COM1X0 0 0 1 1 OCR1X $0000 TOP $0000 TOP Output OC1X L H H L 50 ATMEGA163(L) 1142E-AVR-02/03 ATMEGA163(L) In overflow PWM mode, the table above is only valid for OCR1X = TOP. In PWM mode, the Timer Overflow Flag1, TOV1, is set when the counter advances from $00 00. In overflow PWM mode, the Timer Overflow Flag is set as in Normal Timer/Counter mode. Timer Overflow Interrupt1 operates exactly as in Normal Timer/Counter mode, i.e., it is executed when TOV1 is set provided that Timer Overflow Interrupt1 and global interrupts are enabled. This also applies to the Timer Output Compare1 Flags and interrupts. 8-bit Timer/Counter 2 Figure 37 shows the block diagram for Timer/Counter2. Figure 37. Timer/Counter2 Block Diagram T/C2 OVER- T/C2 COMPARE FLOW IRQ MATCH IRQ 8-BIT DATA BUS 8-BIT ASYNCH T/C2 DATA BUS OCIE1A OCIE2 TICIE1 OCIE1B TOIE2 TOIE1 TOIE0 OCF2 TIMER INT. MASK REGISTER (TIMSK) OCF2 TOV2 TIMER INT. FLAG REGISTER (TIFR) FOC2 TOV2 OCF1A OCF1B TOV1 TOV0 ICF1 T/C2 CONTROL REGISTER (TCCR2) COM21 COM20 PWM2 CTC2 CS22 CS21 CS20 7 TIMER/COUNTER2 (TCNT2) 0 T/C CLEAR T/C CLK SOURCE UP/DOWN CONTROL LOGIC CK PSR2 TOSC1 7 8-BIT COMPARATOR 0 7 OUTPUT COMPARE REGISTER2 (OCR2) 0 ASYNCH. STATUS REGISTER (ASSR) AS2 OCR2UB ICR2UB TC2UB CK PCK2 SYNCH UNIT The 8-bit Timer/Counter2 can select clock source from CK, prescaled CK, or external crystal input TOSC1. It can also be stopped as described in the section "Timer/Counter2 Control Register - TCCR2" on page 52. The Status Flags (Overflow and Compare Match) are found in the Timer/Counter Interrupt Flag Register - TIFR. Control signals are found in the Timer/Counter Control Register TCCR2. The interrupt enable/disable settings are found in "The Timer/Counter Interrupt Mask Register - TIMSK" on page 31. When Timer/Counter2 is externally clocked, the external signal is synchronized with the Oscillator frequency of the CPU. To assure proper sampling of the external clock, the minimum time between two external clock transitions must be at least one internal CPU 51 1142E-AVR-02/03 clock period. The external clock signal is sampled on the rising edge of the internal CPU clock. This module features a high resolution and a high accuracy usage with the lower prescaling opportunities. Similarly, the high prescaling opportunities make this unit useful for lower speed functions or exact timing functions with infrequent actions. Timer/Counter2 can also be used as an 8-bit Pulse Width Modulator. In this mode, Timer/Counter2 and the Output Compare Register serve as a glitch-free, stand-alone PWM with centered pulses. Refer to page 57 for a detailed description on this function. Timer/Counter2 Control Register - TCCR2 Bit $25 ($45) Read/Write Initial Value 7 FOC2 R/W 0 6 PWM2 R/W 0 5 COM21 R/W 0 4 COM20 R/W 0 3 CTC2 R/W 0 2 CS22 R/W 0 1 CS21 R/W 0 0 CS20 R/W 0 TCCR2 * Bit 7 - FOC2: Force Output Compare Writing a logical one to this bit, forces a change in the Compare Match output pin PD7 (OC2) according to the values already set in COM21 and COM20. If the COM21 and COM20 bits are written in the same cycle as FOC2, the new settings will not take effect until next compare match or Forced Output Compare Match occurs. The Force Output Compare bit can be used to change the output pin without waiting for a Compare Match in the Timer. The automatic action programmed in COM21 and COM20 happens as if a Compare Match had occurred, but no interrupt is generated, and the Timer/Counter will not be cleared even if CTC2 is set. The corresponding I/O pin must be set as an output pin for the FOC2 bit to have effect on the pin. The FOC2 bit will always be read as zero. Setting the FOC2 bit has no effect in PWM mode. * Bit 6 - PWM2: Pulse Width Modulator Enable When set (one) this bit enables PWM mode for Timer/Counter2. This mode is described on page 43. * Bits 5, 4 - COM21, COM20: Compare Output Mode, Bits 1 and 0 The COM21 and COM20 control bits determine any output pin action following a Compare Match in Timer/Counter2. Output pin actions affect pin PD7(OC2). This is an alternative function to an I/O port, and the corresponding direction control bit must be set (one) to control an output pin. The control configuration is shown in Table 19. Table 19. Compare Mode Select(1) COM21 0 0 1 1 Note: COM20 0 1 0 1 Description Timer/Counter disconnected from output pin OC2 Toggle the OC2 output line. Clear the OC2 output line (to zero). Set the OC2 output line (to one). 1. In PWM mode, these bits have a different function. Refer to Table 21 on page 55 for a detailed description. 52 ATMEGA163(L) 1142E-AVR-02/03 ATMEGA163(L) * Bit 3 - CTC2: Clear Timer/Counter on Compare Match When the CTC2 control bit is set (one), Timer/Counter2 is Reset to $00 in the CPU clock cycle following a Compare Match. If the control bit is cleared, the Timer/Counter2 continues counting and is unaffected by a Compare Match. When a prescaling of 1 is used, and the Compare Register is set to C, the Timer will count as follows if CTC2 is set: ... | C-1 | C | 0 | 1 |... When the prescaler is set to divide by eight, the Timer will count like this: ... | C-1, C-1, C-1, C-1, C-1, C-1, C-1, C-1 | C, C, C, C, C, C, C, C | 0, 0, 0, 0, 0, 0, 0, 0 | 1, 1, 1, ... In PWM mode, this bit has a different function. If the CTC2 bit is cleared in PWM mode, the Timer/Counter acts as an up/down counter. If the CTC2 bit is set (one), the Timer/Counter wraps when it reaches $FF. Refer to page 54 for a detailed description. * Bits 2, 1, 0 - CS22, CS21, CS20: Clock Select Bits 2, 1, and 0 The Clock Select bits 2, 1, and 0 define the prescaling source of Timer/Counter2. Table 20. Timer/Counter2 Prescale Select CS22 0 0 0 0 1 1 1 1 CS21 0 0 1 1 0 0 1 1 CS20 0 1 0 1 0 1 0 1 Description Timer/Counter2 is stopped. PCK2 PCK2/8 PCK2/32 PCK2/64 PCK2/128 PCK2/256 PCK2/1024 The Stop condition provides a Timer Enable/Disable function. The prescaled modes are scaled directly from the PCK2 clock. Timer/Counter2 - TCNT2 Bit $24 ($44) Read/Write Initial Value 7 MSB R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 6 5 4 3 2 1 0 LSB R/W 0 TCNT2 This 8-bit register contains the value of Timer/Counter2. Timer/Counters2 is implemented as an up or up/down (in PWM mode) counter with read and write access. If the Timer/Counter2 is written to and a clock source is selected, it continues counting in the timer clock cycle following the write operation. 53 1142E-AVR-02/03 Timer/Counter2 Output Compare Register - OCR2 Bit $23 ($43) Read/Write Initial Value 7 MSB R/W 0 6 5 4 3 2 1 0 LSB OCR2 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 The Output Compare Register is an 8-bit read/write register. The Timer/Counter Output Compare Register contains the data to be continuously compared with Timer/Counter2. Actions on compare matches are specified in TCCR2. A software write to the Timer/Counter2 Register blocks compare matches in the next Timer/Counter2 clock cycle. This prevents immediate interrupts when initializing the Timer/Counter2. A Compare Match will set the Compare Interrupt Flag in the CPU clock cycle following the compare event. Timer/Counter2 in PWM Mode When PWM mode is selected, the Timer/Counter2 either wraps (overflows) when it reaches $FF or it acts as an up/down counter. If the up/down mode is selected, the Timer/Counter2 and the Output Compare Register - OCR2 form an 8-bit, free-running, glitch-free, and phase correct PWM with outputs on the PD7(OC2) pin. If the overflow mode is selected, the Timer/Counter2 and the Output Compare Register - OCR2 form an 8-bit, free-running, and glitch-free PWM, operating with twice the speed of the up/down counting mode. PWM Modes (Up/Down and Overflow) The two different PWM modes are selected by the CTC2 bit in the Timer/Counter Control Register - TCCR2. If CTC2 is cleared and PWM mode is selected, the Timer/Counter acts as an up/down counter, counting up from $00 to $FF, where it turns and counts down again to zero before the cycle is repeated. When the counter value matches the contents of the Output Compare Register, the PD7(OC2) pin is set or cleared according to the settings of the COM21/COM20 bits in the Timer/Counter Control Register TCCR2. If CTC2 is set and PWM mode is selected, the Timer/Counters will wrap and start counting from $00 after reaching $FF. The PD7(OC2) pin will be set or cleared according to the settings of COM21/COM20 on a Timer/Counter overflow or when the counter value matches the contents of the Output Compare Register. Refer to Table 21 for details. 54 ATMEGA163(L) 1142E-AVR-02/03 ATMEGA163(L) Table 21. Compare Mode Select in PWM Mode CTC2 0 0 0 COM21 0 0 1 COM20 0 1 0 Effect on Compare Pin Not connected Not connected Cleared on Compare Match, up-counting. Set on Compare Match, down-counting (non-inverted PWM). Cleared on Compare Match, down-counting. Set on Compare Match, up-counting (inverted PWM). Not connected Not connected Cleared on compare match, set on overflow. Set on compare match, cleared on overflow. fTCK0/2/256 fTCK0/2/256 fTCK0/2/510 Frequency 0 1 1 1 1 1 0 0 1 1 1 0 1 0 1 fTCK0/2/510 Note that in PWM mode, the value to be written to the Output Compare Register is first tr an sfe rr ed to a temp o ra ry lo ca tio n , an d the n latc he d in to O CR 2 w h en th e Timer/Counter reaches $FF. This prevents the occurrence of odd-length PWM pulses (glitches) in the event of an unsynchronized OCR2 write. See Figure 38 for examples. Figure 38. Effects of Unsynchronized OCR Latching PWM Output OC2 Synchronized OC2 Latch PWM Output OC2 Unsynchronized OC2 Latch 55 1142E-AVR-02/03 Figure 39. Effects of Unsynchronized OCR Latching in Overflow Mode. Compare Value changes Counter Value Compare Value PWM Output OC2 Synchronized OC2 Latch Compare Value changes Counter Value Compare Value PWM Output OC2 Unsynchronized OC2 Latch Glitch During the time between the write and the latch operation, a read from OCR2 will read the contents of the temporary location. This means that the most recently written value always will read out of OCR2. When the Output Compare Register contains $00 or $FF, and the up/down PWM mode is selected, the output PD7(OC2) is updated to low or high on the next compare match according to the settings of COM21/COM20. This is shown in Table 22. In overflow PWM mode, the output PD7(OC2) is held low or high only when the Output Compare Register contains $FF. Table 22. PWM Outputs OCR2 = $00 or $FF COM21 1 1 1 1 COM20 0 0 1 1 OCR2 $00 $FF $00 $FF Output OC2 L H H L In up/down PWM mode, the Timer Overflow Flag - TOV2, is set when the counter changes direction at $00. In overflow PWM mode, the Timer Overflow Flag is set as in normal Timer/Counter mode. The Timer Overflow Interrupt operates exactly as in normal Timer/Counter mode, i.e., it is executed when TOV2 is set provided that Timer Overflow Interrupt and Global Interrupts are enabled. This also applies to the Timer Output Compare Flag and Interrupt. The frequency of the PWM will be Timer Clock Frequency divided by 510. 56 ATMEGA163(L) 1142E-AVR-02/03 ATMEGA163(L) Asynchronous Status Register - ASSR Bit $22 ($22) Read/Write Initial Value 7 - R 0 6 - R 0 5 - R 0 4 - R 0 3 AS2 R/W 0 2 TCN2UB R 0 1 OCR2UB R 0 0 TCR2UB R 0 ASSR * Bit 7..4 - Res: Reserved Bits These bits are reserved bits in the ATMEGA163 and always read as zero. * Bit 3 - AS2: Asynchronous Timer/Counter2 When AS2 is cleared (zero), Timer/Counter2 is clocked from the internal system clock, CK. When AS2 is set (one), Timer/Counter2 is clocked from the PC6(TOSC1) pin. Pins PC6 and PC7 are connected to a crystal Oscillator and cannot be used as general I/O pins. When the value of this bit is changed, the contents of TCNT2, OCR2, and TCCR2 might be corrupted. * Bit 2 - TCN2UB: Timer/Counter2 Update Busy When Timer/Counter2 operates asynchronously and TCNT2 is written, this bit becomes set (one). When TCNT2 has been updated from the temporary storage register, this bit is cleared (zero) by hardware. A logical zero in this bit indicates that TCNT2 is ready to be updated with a new value. * Bit 1 - OCR2UB: Output Compare Register2 Update Busy When Timer/Counter2 operates asynchronously and OCR2 is written, this bit becomes set (one). When OCR2 has been updated from the temporary storage register, this bit is cleared (zero) by hardware. A logical zero in this bit indicates that OCR2 is ready to be updated with a new value. * Bit 0 - TCR2UB: Timer/Counter Control Register2 Update Busy When Timer/Counter2 operates asynchronously and TCCR2 is written, this bit becomes set (one). When TCCR2 has been updated from the temporary storage register, this bit is cleared (zero) by hardware. A logical zero in this bit indicates that TCCR2 is ready to be updated with a new value. If a write is performed to any of the three Timer/Counter2 Registers while its update busy flag is set (one), the updated value might get corrupted and cause an unintentional interrupt to occur. The mechanisms for reading TCNT2, OCR2, and TCCR2 are different. When reading TCNT2, the actual timer value is read. When reading OCR2 or TCCR2, the value in the temporary storage register is read. 57 1142E-AVR-02/03 Asynchronous Operation of Timer/Counter2 When Timer/Counter2 operates asynchronously, some considerations must be taken. * Warning: When switching between asynchronous and synchronous clocking of Timer/Counter2, the Timer Registers TCNT2, OCR2, and TCCR2 might be corrupted. A safe procedure for switching clock source is: 1. Disable the Timer/Counter2 interrupts by clearing OCIE2 and TOIE2. 2. Select clock source by setting AS2 as appropriate. 3. Write new values to TCNT2, OCR2, and TCCR2. 4. To switch to asynchronous operation: Wait for TCN2UB, OCR2UB, and TCR2UB. 5. Clear the Timer/Counter2 Interrupt Flags. 6. Enable interrupts, if needed. * The Oscillator is optimized for use with a 32.768 kHz watch crystal. Applying an external clock to the TOSC1 pin may result in incorrect Timer/Counter2 operation. The CPU main clock frequency must be more than four times the Oscillator frequency. When writing to one of the registers TCNT2, OCR2, or TCCR2, the value is transferred to a temporary register, and latched after two positive edges on TOSC1. The user should not write a new value before the contents of the temporary register have been transferred to its destination. Each of the three mentioned registers have their individual temporary register, which means that e.g. writing to TCNT2 does not disturb an OCR2 write in progress. To detect that a transfer to the destination register has taken place, the Asynchronous Status Register - ASSR has been implemented. When entering Power-save mode after having written to TCNT2, OCR2, or TCCR2, the user must wait until the written register has been updated if Timer/Counter2 is used to wake up the device. Otherwise, the MCU will enter sleep mode before the changes are effective. This is particularly important if the Output Compare2 interrupt is used to wake up the device, since the output compare function is disabled during writing to OCR2 or TCNT2. If the write cycle is not finished, and the MCU enters sleep mode before the OCR2UB bit returns to zero, the device will never receive a compare match interrupt, and the MCU will not wake up. If Timer/Counter2 is used to wake the device up from Power-save mode, precautions must be taken if the user wants to re-enter Power-save mode: The interrupt logic needs one TOSC1 cycle to be Reset. If the time between wake-up and re-entering Power-save mode is less than one TOSC1 cycle, the interrupt will not occur, and the device will fail to wake up. If the user is in doubt whether the time before re-entering Power-save is sufficient, the following algorithm can be used to ensure that one TOSC1 cycle has elapsed: 1. Write a value to TCCR2, TCNT2, or OCR2. 2. Wait until the corresponding Update Busy Flag in ASSR returns to zero. 3. Enter Power-save mode. * When the asynchronous operation is selected, the 32.768 kHz Oscillator for Timer/Counter2 is always running, except in Power-down mode. After a Power-up Reset or Wake-up from Power-down, the user should be aware of the fact that this Oscillator might take as long as one second to stabilize. The user is advised to wait for at least one second before using Timer/Counter2 after Power-up or wake-up from Power-down. The contents of all Timer/Counter2 Registers must be considered lost after a wake-up from Power-down due to unstable clock signal upon startup. Description of wake-up from Power-save mode when the Timer is clocked asynchronously: When the interrupt condition is met, the wake-up process is started * * * * 58 ATMEGA163(L) 1142E-AVR-02/03 ATMEGA163(L) on the following cycle of the timer clock, that is, the timer is always advanced by at least one before the processor can read the counter value. After wake-up, the MCU is halted for four clock cycles, it executes the interrupt routine, and resumes execution from the instruction following SLEEP. * During asynchronous operation, the synchronization of the interrupt flags for the asynchronous timer takes three processor cycles plus one timer cycle. The timer is therefore advanced by at least one before the processor can read the timer value causing the setting of the Interrupt Flag. The output compare pin is changed on the timer clock and is not synchronized to the processor clock. After waking up from Power-save mode with the asynchronous timer enabled, there will be a short interval in which TCNT2 will read as the same value as before Powersave mode was entered. After an edge on the asynchronous clock, TCNT2 will read correctly (The compare and overflow functions of the Timer are not affected by this behavior.). Safe procedure to ensure that the correct value is read: 1. Write any value to either of the registers OCR2 or TCCR2. 2. Wait for the corresponding Update Busy Flag to be cleared. 3. Read TCNT2. Note that OCR2 and TCCR2 are never modified by hardware, and will always read correctly. * 59 1142E-AVR-02/03 Watchdog Timer The Watchdog Timer is clocked from a separate On-chip Oscillator which runs at 1 MHz. This is the typical value at VCC = 5V. See characterization data for typical values at other VCC levels. By controlling the Watchdog Timer prescaler, the Watchdog Reset interval can be adjusted as shown in Table 23 on page 61. The WDR - Watchdog Reset - instruction resets the Watchdog Timer. Eight different clock cycle periods can be selected to determine the reset period. If the reset period expires without another Watchdog Reset, the ATMEGA163 resets and executes from the Reset Vector. For timing details on the Watchdog Reset, refer to page 28. To prevent unintentional disabling of the Watchdog, a special turn-off sequence must be followed when the Watchdog is disabled. Refer to the description of the Watchdog Timer Control Register for details. Figure 40. Watchdog Timer OSCILLATOR 1 MHz at VCC = 5V The Watchdog Timer Control Register - WDTCR Bit $21 ($41) Read/Write Initial Value 7 - R 0 6 - R 0 5 - R 0 4 WDTOE R/W 0 3 WDE R/W 0 2 WDP2 R/W 0 1 WDP1 R/W 0 0 WDP0 R/W 0 WDTCR * Bits 7..5 - Res: Reserved Bits These bits are reserved bits in the ATMEGA163 and will always read as zero. * Bit 4 - WDTOE: Watchdog Turn-off Enable This bit must be set (one) when the WDE bit is cleared. Otherwise, the Watchdog will not be disabled. Once set, hardware will clear this bit to zero after four clock cycles. Refer to the description of the WDE bit for a Watchdog disable procedure. * Bit 3 - WDE: Watchdog Enable When the WDE is set (one) the Watchdog Timer is enabled, and if the WDE is cleared (zero) the Watchdog Timer function is disabled. WDE can only be cleared if the WDTOE bit is set(one). To disable an enabled Watchdog Timer, the following procedure must be followed: 60 ATMEGA163(L) 1142E-AVR-02/03 ATMEGA163(L) 1. In the same operation, write a logical one to WDTOE and WDE. A logical one must be written to WDE even though it is set to one before the disable operation starts. 2. Within the next four clock cycles, write a logical 0 to WDE. This disables the Watchdog. * Bits 2..0 - WDP2, WDP1, WDP0: Watchdog Timer Prescaler 2, 1, and 0 The WDP2, WDP1, and WDP0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is enabled. The different prescaling values and their corresponding Timeout Periods are shown in Table 23. Table 23. Watchdog Timer Prescale Select WDP2 0 0 0 0 1 1 1 1 WDP1 0 0 1 1 0 0 1 1 WDP0 0 1 0 1 0 1 0 1 Number of WDT Oscillator Cycles 16K cycles 32K cycles 64K cycles 128K cycles 256K cycles 512K cycles 1,024K cycles 2,048K cycles Typical Time-out at VCC = 3.0V 47 ms 94 ms 0.19 s 0.38 s 0.75 s 1.5 s 3.0 s 6.0 s Typical Time-out at VCC = 5.0V 15 ms 30 ms 60 ms 0.12 s 0.24 s 0.49 s 0.97 s 1.9 s 61 1142E-AVR-02/03 EEPROM Read/Write Access The EEPROM Access Registers are accessible in the I/O space. The write access time is in the range of 1.9 - 3.8 ms, depending on the VCC voltages. See Table 24 for details. A self-timing function, however, lets the user software detect when the next byte can be written. If the user code contains code that writes the EEPROM, some precautions must be taken. In heavily filtered power supplies, VCC is likely to rise or fall slowly on Power-up/down. This causes the device for some period of time to run at a voltage lower than specified as minimum for the clock frequency used. CPU operation under these conditions is likely to cause the Program Counter to perform unintentional jumps and potentially execute the EEPROM write code. To secure EEPROM integrity, the user is advised to use an External under-voltage Reset circuit or the internal BOD in this case. In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. Refer to the description of the EEPROM Control Register for details on this. When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next instruction is executed. The EEPROM Address Register - EEARH and EEARL Bit $1F ($3F) $1E ($3E) 15 - EEAR7 7 14 - EEAR6 6 R R/W 0 X 13 - EEAR5 5 R R/W 0 X 12 - EEAR4 4 R R/W 0 X 11 - EEAR3 3 R R/W 0 X 10 - EEAR2 2 R R/W 0 X 9 - EEAR1 1 R R/W 0 X 8 EEAR8 EEAR0 0 R/W R/W X X EEARH EEARL Read/Write R R/W Initial Value 0 X * Bits 15..9 - Res: Reserved Bits These bits are reserved bits in the ATMEGA163 and will always read as zero. * Bits 8..0 - EEAR8..0: EEPROM Address The EEPROM Address Registers - EEARH and EEARL - specify the EEPROM address in the 512 bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and 511. The initial value of EEAR is undefined. A proper value must be written before the EEPROM may be accessed. The EEPROM Data Register - EEDR Bit $1D ($3D) Read/Write Initial Value 7 MSB R/W 0 6 5 4 3 2 1 0 LSB EEDR R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 * Bits 7..0 - EEDR7.0: EEPROM Data For the EEPROM write operation, the EEDR Register contains the data to be written to the EEPROM in the address given by the EEAR Register. For the EEPROM read operation, the EEDR contains the data read out from the EEPROM at the address given by EEAR. 62 ATMEGA163(L) 1142E-AVR-02/03 ATMEGA163(L) The EEPROM Control Register - EECR Bit $1C ($3C) Read/Write Initial Value 7 - R 0 6 - R 0 5 - R 0 4 - R 0 3 EERIE R/W 0 2 EEMWE R/W 0 1 EEWE R/W 0 0 EERE R/W 0 EECR * Bits 7..4 - Res: Reserved Bits These bits are reserved bits in the ATMEGA163 and will always read as zero. * Bit 3 - EERIE: EEPROM Ready Interrupt Enable When the I bit in SREG and EERIE are set (one), the EEPROM Ready Interrupt is enabled. When cleared (zero), the interrupt is disabled. The EEPROM Ready interrupt generates a constant interrupt when EEWE is cleared (zero). * Bit 2 - EEMWE: EEPROM Master Write Enable The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written. When EEMWE is set(one) setting EEWE will write data to the EEPROM at the selected address If EEMWE is zero, setting EEWE will have no effect. When EEMWE has been set (one) by software, hardware clears the bit to zero after four clock cycles. See the description of the EEWE bit for an EEPROM write procedure. * Bit 1 - EEWE: EEPROM Write Enable The EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When address and data are correctly set up, the EEWE bit must be set to write the value into the EEPROM. The EEMWE bit must be set when the logical one is written to EEWE, otherwise no EEPROM write takes place. The following procedure should be followed when writing the EEPROM (the order of steps 2 and 3 is not essential): 1. Wait until EEWE becomes zero. 2. Write new EEPROM address to EEAR (optional). 3. Write new EEPROM data to EEDR (optional). 4. Write a logical one to the EEMWE bit in EECR. 5. Within four clock cycles after setting EEMWE, write a logical one to EEWE. Caution: An interrupt between step 4 and step 5 will make the write cycle fail, since the EEPROM Master Write Enable will time-out. If an interrupt routine accessing the EEPROM is interrupting another EEPROM access, the EEAR or EEDR Register will be modified, causing the interrupted EEPROM access to fail. It is recommended to have the Global Interrupt Flag cleared during the four last steps to avoid these problems. When the write access time (see Table 24) has elapsed, the EEWE bit is cleared (zero) by hardware. The user software can poll this bit and wait for a zero before writing the next byte. When EEWE has been set, the CPU is halted for four cycles before the next instruction is executed. * Bit 0 - EERE: EEPROM Read Enable The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct address is set up in the EEAR Register, the EERE bit must be set. When the EERE bit is cleared (zero) by hardware, requested data is found in the EEDR Register. The EEPROM read access takes one instruction, and there is no need to poll the EERE bit. When EERE has been set, the CPU is halted for two cycles before the next instruction is executed. 63 1142E-AVR-02/03 The user should poll the EEWE bit before starting the read operation. If a write operation is in progress, it is not possible to set the EERE bit, nor to change the EEAR Register. The calibrated Oscillator is used to time the EEPROM accesses. Table 24 lists the typical programming time for EEPROM access from the CPU Table 24. EEPROM Programming Time. Symbol EEPROM write (from CPU) Number of Calibrated RC Oscillator Cycles 2048 Min Programmingn Time 1.9 ms Max Programming Time 3.8 ms Preventing EEPROM Corruption During periods of low VCC, the EEPROM data can be corrupted because the supply voltage is too low for the CPU and the EEPROM to operate properly. These issues are the same as for board level systems using the EEPROM, and the same design solutions should be applied. An EEPROM data corruption can be caused by two situations when the voltage is too low. First, a regular write sequence to the EEPROM requires a minimum voltage to operate correctly. Secondly, the CPU itself can execute instructions incorrectly, if the supply voltage for executing instructions is too low. EEPROM data corruption can easily be avoided by following these design recommendations (one is sufficient): 1. Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can be done by enabling the internal Brown-out Detector (BOD) if the operating voltage matches the detection level. If not, an external low VCC Reset Protection circuit can be used. If a Reset occurs while a write operation is in progress, the write operation will be completed provided that the power supply is voltage is sufficient. 2. Keep the AVR core in Power-down Sleep Mode during periods of low VCC. This will prevent the CPU from attempting to decode and execute instructions, effectively protecting the EEPROM Registers from unintentional writes. 3. Store constants in Flash memory if the ability to change memory contents from software is not required. Flash memory can not be updated by the CPU unless the boot loader software supports writing to the Flash and the Boot Lock bits are configured so that writing to the Flash memory from CPU is allowed. See "Boot Loader Support" on page 134 for details. 64 ATMEGA163(L) 1142E-AVR-02/03 ATMEGA163(L) Serial Peripheral Interface - SPI The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the ATMEGA163 and peripheral devices or between several AVR devices. The ATMEGA163 SPI includes the following features: * Full-duplex, Three-wire Synchronous Data Transfer * Master or Slave Operation * LSB First or MSB First Data Transfer * Seven Programmable Bit Rates * End of Transmission Interrupt Flag * Write Collision Flag Protection * Wake-up from Idle Mode * Double Speed (CK/2) Master SPI Mode Figure 41. SPI Block Diagram DIVIDER /2/4/8/16/32/64/128 SPI2X The interconnection between Master and Slave CPUs with SPI is shown in Figure 42. The PB7(SCK) pin is the clock output in the Master mode and the clock input in the Slave mode. Writing to the SPI Data Register of the Master CPU starts the SPI clock generator, and the data written shifts out of the PB5(MOSI) pin and into the PB5(MOSI) pin of the Slave CPU. After shifting one byte, the SPI Clock Generator stops, setting the end of Transmission Flag (SPIF). If the SPI Interrupt Enable bit (SPIE) in the SPCR Register is set, an interrupt is requested. The Slave Select input, PB4(SS), is set low to select an individual Slave SPI device. The two Shift Registers in the Master and the Slave can be considered as one distributed 16-bit circular Shift Register. This is shown in Figure 42. When data is shifted from the Master to the Slave, data is also shifted in SPI2X 65 1142E-AVR-02/03 the opposite direction, simultaneously. During one shift cycle, data in the Master and the Slave is interchanged. Figure 42. SPI Master-Slave Interconnection The system is single buffered in the transmit direction and double buffered in the receive direction. This means that bytes to be transmitted cannot be written to the SPI Data Register before the entire shift cycle is completed. When receiving data, however, a received character must be read from the SPI Data Register before the next character has been completely shifted in. Otherwise, the first byte is lost. When the SPI is enabled, the data direction of the MOSI, MISO, SCK, and SS pins is overridden according to Table 25. Table 25. SPI Pin Overrides(1) Pin MOSI MISO SCK SS Note: Direction, Master SPI User Defined Input User Defined User Defined Direction, Slave SPI Input User Defined Input Input 1. See "Alternate Functions Of PORTB" on page 118 for a detailed description of how to define the direction of the user defined SPI pins. SS Pin Functionality When the SPI is configured as a Master (MSTR in SPCR is set), the user can determine the direction of the SS pin. If SS is configured as an output, the pin is a general output pin which does not affect the SPI system. If SS is configured as an input, it must be held high to ensure Master SPI operation. If the SS pin is driven low by peripheral circuitry when the SPI is configured as a Master with the SS pin defined as an input, the SPI system interprets this as another Master selecting the SPI as a Slave and starting to send data to it. To avoid bus contention, the SPI system takes the following actions: 1. The MSTR bit in SPCR is cleared and the SPI system becomes a Slave. As a result of the SPI becoming a Slave, the MOSI and SCK pins become inputs. 2. The SPIF Flag in SPSR is set, and if the SPI interrupt is enabled, and the I-bit in SREG is set, the interrupt routine will be executed. Thus, when interrupt-driven SPI transmission is used in Master mode, and there exists a possibility that SS is driven low, the interrupt should always check that the MSTR bit is still set. If the MSTR bit has been cleared by a slave select, it must be set by the user to re-enable SPI Master mode. 66 ATMEGA163(L) 1142E-AVR-02/03 ATMEGA163(L) When the SPI is configured as a Slave, the SS pin is always input. When SS is held low, the SPI is activated, and MISO becomes an output if configured so by the user. All other pins are inputs. When SS is driven high, all pins are inputs, and the SPI is passive, which means that it will not receive incoming data. Note that the SPI logic will be Reset once the SS pin is driven high. If the SS pin is driven high during a transmission, the SPI will stop sending and receiving immediately and both data received and data sent must be considered as lost. Data Modes There are four combinations of SCK phase and polarity with respect to serial data, which are determined by control bits CPHA and CPOL. The SPI data transfer formats are shown in Figure 43 and Figure 44. Figure 43. SPI Transfer Format with CPHA = 0 and DORD = 0 Figure 44. SPI Transfer Format with CPHA = 1 and DORD = 0 SPI Control Register - SPCR Bit $0D ($2D) Read/Write Initial Value 7 SPIE R/W 0 6 SPE R/W 0 5 DORD R/W 0 4 MSTR R/W 0 3 CPOL R/W 0 2 CPHA R/W 0 1 SPR1 R/W 0 0 SPR0 R/W 0 SPCR * Bit 7 - SPIE: SPI Interrupt Enable This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and the if the Global Interrupt Enable bit in SREG is set. * Bit 6 - SPE: SPI Enable When the SPE bit is set (one), the SPI is enabled. This bit must be set to enable any SPI operations. 67 1142E-AVR-02/03 * Bit 5 - DORD: Data Order When the DORD bit is set (one), the LSB of the data word is transmitted first. When the DORD bit is cleared (zero), the MSB of the data word is transmitted first. * Bit 4 - MSTR: Master/Slave Select This bit selects Master SPI mode when set (one), and Slave SPI mode when cleared (zero). If SS is configured as an input and is driven low while MSTR is set, MSTR will be cleared, and SPIF in SPSR will become set. The user will then have to set MSTR to reenable SPI Master mode. * Bit 3 - CPOL: Clock Polarity When this bit is set (one), SCK is high when idle. When CPOL is cleared (zero), SCK is low when idle. Refer to Figure 43 and Figure 44 for additional information. * Bit 2 - CPHA: Clock Phase Refer to Figure 43 and Figure 44 for the functionality of this bit. * Bits 1, 0 - SPR1, SPR0: SPI Clock Rate Select 1 and 0 These two bits control the SCK rate of the device configured as a Master. SPR1 and SPR0 have no effect on the Slave. The relationship between SCK and the Oscillator Clock frequency fck is shown in the following table: Table 26. Relationship Between SCK and the Oscillator Frequency SPI2X 0 0 0 0 1 1 1 1 SPR1 0 0 1 1 0 0 1 1 SPR0 0 1 0 1 0 1 0 1 SCK Frequency fck/4 fck/16 fck/64 fck/128 fck/2 fck/8 fck/32 fck/64 3 - R 0 2 - R 0 1 - R 0 0 SPI2X R/W 0 SPSR The SPI Status Register - SPSR Bit $0E ($2E) Read/Write Initial Value 7 SPIF R 0 6 WCOL R 0 5 - R 0 4 - R 0 * Bit 7 - SPIF : SPI Interrupt Flag When a serial transfer is complete, the SPIF bit is set (one) and an interrupt is generated if SPIE in SPCR is set (one) and global interrupts are enabled. If SS is an input and is driven low when the SPI is in Master mode, this will also set the SPIF Flag. SPIF is cleared by hardware when executing the corresponding Interrupt Handling Vector. Alternatively, the SPIF bit is cleared by first reading the SPI Status Register with SPIF set (one), then accessing the SPI Data Register (SPDR). 68 ATMEGA163(L) 1142E-AVR-02/03 ATMEGA163(L) * Bit 6 - WCOL : Write COLlision Flag The WCOL bit is set if the SPI Data Register (SPDR) is written during a data transfer. The WCOL bit (and the SPIF bit) are cleared (zero) by first reading the SPI Status Register with WCOL set (one), and then accessing the SPI Data Register. * Bit 5..1 - Res: Reserved Bits These bits are reserved bits in the ATMEGA163 and will always read as zero. * Bit 0 - SPI2X: Double SPI Speed Bit When this bit is set (one) the SPI speed (SCK Frequency) will be doubled when the SPI is in Master mode (see Table 26). This means that the minimum SCK period will be two CPU clock periods. When the SPI is configured as Slave, the SPI is only guaranteed to work at fck/4 or lower. The SPI interface on the ATMEGA163 is also used for Program memory and EEPROM downloading or uploading. See page 155 for Serial Programming and verification. The SPI Data Register - SPDR Bit $0F ($2F) Read/Write Initial Value 7 MSB R/W X R/W X R/W X R/W X R/W X R/W X R/W X 6 5 4 3 2 1 0 LSB R/W X Undefined SPDR The SPI Data Register is a read/write register used for data transfer between the Register File and the SPI Shift Register. Writing to the register initiates data transmission. Reading the register causes the Shift Register Receive buffer to be read. 69 1142E-AVR-02/03 UART The ATMEGA163 features a full duplex (separate Receive and Transmit Registers) Universal Asynchronous Receiver and Transmitter (UART). The main features are: * Baud Rate Generator Generates any Baud Rate * High Baud Rates at Low XTAL Frequencies * 8 or 9 Bits Data * Noise Filtering * OverRun Detection * Framing Error Detection * False Start Bit Detection * Three Separate Interrupts on TX Complete, TX Data Register Empty, and RX Complete * Multi-processor Communication Mode * Double Speed UART Mode A block schematic of the UART transmitter is shown in Figure 45. Figure 45. UART Transmitter Data Transmission Data transmission is initiated by writing the data to be transmitted to the UART I/O Data Register, UDR. Data is transferred from UDR to the Transmit Shift Register when: * * A new character has been written to UDR after the stop bit from the previous character has been shifted out. The Shift Register is loaded immediately. A new character has been written to UDR before the stop bit from the previous character has been shifted out. The Shift Register is loaded when the stop bit of the character currently being transmitted has been shifted out. 70 ATMEGA163(L) 1142E-AVR-02/03 ATMEGA163(L) When data is transferred from UDR to the Shift Register, the UDRE (UART Data Register Empty) bit in the UART Status Register, USR, is set. When this bit is set (one), the UART is ready to receive the next character. At the same time as the data is transferred from UDR to the 10(11)-bit Shift Register, bit 0 of the Shift Register is cleared (start bit) and bit 9 or 10 is set (stop bit). If 9-bit data word is selected (the CHR9 bit in the UART Control Register, UCR is set), the TXB8 bit in UCR is transferred to bit 9 in the Transmit Shift Register. On the Baud Rate clock following the transfer operation to the Shift Register, the start bit is shifted out on the TXD pin. Then follows the data, LSB first. When the stop bit has been shifted out, the Shift Register is loaded if any new data has been written to the UDR during the transmission. During loading, UDRE is set. If there is no new data in the UDR Register to send when the stop bit is shifted out, the UDRE Flag will remain set until UDR is written again. When no new data has been written, and the stop bit has been present on TXD for one bit length, the Transmit Complete Flag, TXC, in USR is set. The TXEN bit in UCR enables the UART transmitter when set (one). When this bit is cleared (zero), the PD1 pin can be used for general I/O. When TXEN is set, the UART Transmitter will be connected to PD1, which is forced to be an output pin regardless of the setting of the DDD1 bit in DDRD. 71 1142E-AVR-02/03 Data Reception Figure 46 shows a block diagram of the UART Receiver Figure 46. UART Receiver The Receiver front-end logic samples the signal on the RXD pin at a frequency 16 times the baud rate. While the line is idle, one single sample of logical zero will be interpreted as the falling edge of a start bit, and the start bit detection sequence is initiated. Let sample 1 denote the first zero-sample. Following the 1 to 0-transition, the receiver samples the RXD pin at samples 8, 9, and 10. If two or more of these three samples are found to be logical ones, the start bit is rejected as a noise spike and the receiver starts looking for the next 1 to 0-transition. If however, a valid start bit is detected, sampling of the data bits following the start bit is performed. These bits are also sampled at samples 8, 9, and 10. The logical value found in at least two of the three samples is taken as the bit value. All bits are shifted into the Transmitter Shift Register as they are sampled. Sampling of an incoming character is shown in Figure 47. Note that the description above is not valid when the UART transmission speed is doubled. See "Double Speed Transmission" on page 78 for a detailed description. 72 ATMEGA163(L) 1142E-AVR-02/03 ATMEGA163(L) Figure 47. Sampling Received Data(1) Note: 1. This figure is not valid when the UART speed is doubled. See "Double Speed Transmission" on page 78 for a detailed description. When the stop bit enters the Receiver, the majority of the three samples must be one to accept the stop bit. If two or more samples are logical zeros, the Framing Error (FE) Flag in the UART Status Register (USR) is set. Before reading the UDR Register, the user should always check the FE bit to detect Framing Errors. Whether or not a valid stop bit is detected at the end of a character reception cycle, the data is transferred to UDR and the RXC Flag in USR is set. UDR is in fact two physically separate registers, one for transmitted data and one for received data. When UDR is read, the Receive Data Register is accessed, and when UDR is written, the Transmit Data Register is accessed. If 9-bit data word is selected (the CHR9 bit in the UART Control Register, UCR is set), the RXB8 bit in UCR is loaded with bit nine in the Transmit Shift Register when data is transferred to UDR. If, after having received a character, the UDR Register has not been read since the last receive, the OverRun (OR) Flag in UCR is set. This means that the last data byte shifted into to the Shift Register could not be transferred to UDR and has been lost. The OR bit is buffered, and is updated when the valid data byte in UDR is read. Thus, the user should always check the OR bit when reading the UDR Register in order to detect any overruns if the baud rate is high or CPU load is high. When the RXEN bit in the UCR Register is cleared (zero), the receiver is disabled. This means that the PD0 pin can be used as a general I/O pin. When RXEN is set, the UART Receiver will be connected to PD0, which is forced to be an input pin regardless of the setting of the DDD0 bit in DDRD. When PD0 is forced to input by the UART, the PORTD0 bit can still be used to control the pull-up resistor on the pin. When the CHR9 bit in the UCR Register is set, transmitted and received characters are 9-bit long plus start and stop bits. The ninth data bit to be transmitted is the TXB8 bit in UCR Register. This bit must be set to the wanted value before a transmission is initated by writing to the UDR Register. The 9th data bit received is the RXB8 bit in the UCR Register. It is important that the Status Register (USR) always is read before the Data Register (UDR). The Data Register should be read only once for each received byte. Otherwise, the Status Register (USR) might get updated with incorrect values. Multi-processor Communication Mode The Multi-Processor Communication mode enables several Slave MCUs to receive data from a Master MCU. This is done by first decoding an address byte to find out which MCU has been addressed. If a particular Slave MCU has been addressed, it will receive the following data bytes as normal, while the other Slave MCUs will ignore the data bytes until another address byte is received. For an MCU to act as a Master MCU, it should enter 9-bit transmission mode (CHR9 in UCSRB set). The ninth bit must be one to indicate that an address byte is being transmitted, and zero to indicate that a data byte is being transmitted. For the Slave MCUs, the mechanism appears slightly differently for 8-bit and 9-bit reception mode. In 8-bit reception mode (CHR9 in UCSRB cleared), the stop bit is one for an address byte and zero for a data byte. In 9-bit reception mode (CHR9 in UCSRB 73 1142E-AVR-02/03 set), the 9th bit is one for an address byte and zero for a data byte, whereas the stop bit is always high. The following procedure should be used to exchange data in Multi-Processor Communication mode: 1. All Slave MCUs are in Multi-Processor Communication mode (MPCM in UCSRA is set). 2. The Master MCU sends an address byte, and all slaves receive and read this byte. In the Slave MCUs, the RXC Flag in UCSRA will be set as normal. 3. Each Slave MCU reads the UDR Register and determines if it has been selected. If so, it clears the MPCM bit in UCSRA, otherwise it waits for the next address byte. 4. For each received data byte, the receiving MCU will set the Receive Complete Flag (RXC in UCSRA). In 8-bit mode, the receiving MCU will also generate a Framing Error (FE in UCSRA set), since the stop bit is zero. The other slave MCUs, which still have the MPCM bit set, will ignore the data byte. In this case, the UDR Register and the RXC or FE Flags will not be affected. 5. After the last byte has been transferred, the process repeats from step 2. UART Control UART I/O Data Register - UDR Bit $0C ($2C) Read/Write Initial Value 7 MSB R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 6 5 4 3 2 1 0 LSB R/W 0 UDR The UDR Register is actually two physically separate registers sharing the same I/O address. When writing to the register, the UART Transmit Data Register is written. When reading from UDR, the UART Receive Data Register is read. UART Control and Status Register A - UCSRA Bit $0B ($2B) Read/Write Initial Value 7 RXC r 0 6 TXC R/W 0 5 UDRE R 0 4 FE R 0 3 OR R 0 2 - R 0 1 U2X R/W 0 0 MPCM R/W 0 UCSRA * Bit 7 - RXC: UART Receive Complete This bit is set (one) when a received character is transferred from the Receiver Shift Register to UDR. The bit is set regardless of any detected framing errors. When the RXCIE bit in UCR is set, the UART Receive Complete interrupt will be executed when RXC is set(one). RXC is cleared by reading UDR. When interrupt-driven data reception is used, the UART Receive Complete Interrupt routine must read UDR in order to clear RXC, otherwise a new interrupt will occur once the interrupt routine terminates. * Bit 6 - TXC: UART Transmit Complete This bit is set (one) when the entire character (including the stop bit) in the Transmit Shift Register has been shifted out and no new data has been written to UDR. This Flag is especially useful in half-duplex communications interfaces, where a transmitting application must enter receive mode and free the communications bus immediately after completing the transmission. 74 ATMEGA163(L) 1142E-AVR-02/03 ATMEGA163(L) When the TXCIE bit in UCR is set, setting of TXC causes the UART Transmit Complete interrupt to be executed. TXC is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, the TXC bit is cleared (zero) by writing a logical one to the bit. * Bit 5 - UDRE: UART Data Register Empty This bit is set (one) when a character written to UDR is transferred to the Transmit Shift Register. Setting of this bit indicates that the transmitter is ready to receive a new character for transmission. When the UDRIE bit in UCR is set, the UART Transmit Complete interrupt to be executed as long as UDRE is set. UDRE is cleared by writing UDR. When interrupt-driven data transmittal is used, the UART Data Register Empty Interrupt routine must write UDR in order to clear UDRE, otherwise a new interrupt will occur once the interrupt routine terminates. UDRE is set (one) during reset to indicate that the transmitter is ready. * Bit 4 - FE: Framing Error This bit is set if a Framing Error condition is detected, i.e. when the stop bit of an incoming character is zero. The FE bit is cleared when the stop bit of received data is one. * Bit 3 - OR: OverRun This bit is set if an Overrun condition is detected, i.e., when a character already present in the UDR Register is not read before the next character has been shifted into the Receiver Shift Register. The OR bit is buffered, which means that it will be set once the valid data still in UDR is read. The OR bit is cleared (zero) when data is received and transferred to UDR. * Bit 2 - Res: Reserved Bit This bit is a reserved bit in the ATMEGA163 and will always read as zero. * Bits 1 - U2X: Double the UART Transmission Speed Setting this bit will reduce the division of the baud rate generator clock from 16 to 8, effectively doubling the transfer speed at the expense of robustness. For a detailed description, see "Double Speed Transmission" on page 78. * Bit 0 - MPCM: Multi-processor Communication Mode This bit is used to enter Multi-Processor Communication mode. The bit is set when the slave MCU waits for an address byte to be received. When the MCU has been addressed, the MCU switches off the MPCM bit, and starts data reception. For a detailed description, see "Multi-processor Communication Mode" on page 73. 75 1142E-AVR-02/03 UART Control and Status Register B - UCSRB Bit $0A ($2A) Read/Write Initial Value 7 RXCIE R/W 0 6 TXCIE R/W 0 5 UDRIE R/W 0 4 RXEN R/W 0 3 TXEN R/W 0 2 CHR9 R/W 0 1 RXB8 R 1 0 TXB8 W 0 UCSRB * Bit 7 - RXCIE: RX Complete Interrupt Enable When this bit is set (one), a setting of the RXC bit in USR will cause the Receive Complete interrupt routine to be executed provided that global interrupts are enabled. * Bit 6 - TXCIE: TX Complete Interrupt Enable When this bit is set (one), a setting of the TXC bit in USR will cause the Transmit Complete interrupt routine to be executed provided that global interrupts are enabled. * Bit 5 - UDRIE: UART Data Register Empty Interrupt Enable When this bit is set (one), a setting of the UDRE bit in USR will cause the UART Data Register Empty interrupt routine to be executed provided that global interrupts are enabled. * Bit 4 - RXEN: Receiver Enable This bit enables the UART Receiver when set (one). When the Receiver is disabled, the RXC, OR, and FE Status Flags cannot become set. If these flags are set, turning off RXEN does not cause them to be cleared. * Bit 3 - TXEN: Transmitter Enable This bit enables the UART Transmitter when set (one). When disabling the Transmitter while transmitting a character, the Transmitter is not disabled before the character in the Shift Register plus any following character in UDR has been completely transmitted. * Bit 2 - CHR9: 9-bit Characters When this bit is set (one) transmitted and received characters are 9-bit long plus start and stop bits. The ninth bit is read and written by using the RXB8 and TXB8 bits in UCR, respectively. The ninth data bit can be used as an extra stop bit or a parity bit. * Bit 1 - RXB8: Receive Data Bit 8 When CHR9 is set (one), RXB8 is the ninth data bit of the received character. * Bit 0 - TXB8: Transmit Data Bit 8 When CHR9 is set (one), TXB8 is the ninth data bit in the character to be transmitted. Baud Rate Generator The Baud Rate generator is a frequency divider which generates baud-rates according to the following equation: f CK BAUD = --------------------------------16(UBR + 1 ) * * * BAUD = Baud Rate fCK= Crystal Clock frequency UBR = Contents of the UBRRHI and UBRR Registers, (0 - 4095) 76 ATMEGA163(L) 1142E-AVR-02/03 ATMEGA163(L) * Note that this equation is not valid when the UART transmission speed is doubled. See "Double Speed Transmission" on page 78 for a detailed description. For standard crystal frequencies, the most commonly used baud rates can be generated by using the UBR settings in Table 27. UBR values which yield an actual baud rate differing less than 2% from the target baud rate, are bold in the table. However, using baud rates that have more than 1% error is not recommended. High error ratings give less noise resistance. Table 27. UBR Settings at Various Crystal Frequencies Baud R ate 2400 4800 9600 14400 19200 28800 38400 57600 76800 11520 0 Baud R ate 2400 4800 9600 14400 19200 28800 38400 57600 76800 11520 0 Baud R ate 2400 4800 9600 14400 19200 28800 38400 57600 76800 11520 0 1 MHz % Error UBR= UBR= UBR= UBR= UBR= UBR= UBR= UBR= UBR= UBR= 25 12 6 3 2 1 1 0 0 0 1,84 MHz % Erro r 47 23 11 7 5 3 2 1 1 0 2 MHz 51 25 12 8 6 3 2 1 1 0 % Error 2,458 MHz % Error 63 31 15 10 7 4 3 2 1 0 0,0 0,0 0,0 3,1 0,0 6,3 0,0 1 2,5 0,0 2 5,0 0,2 U BR = 0,2 U BR = 7,5 U BR = 7,8 U BR = 7,8 U BR = 7,8 U BR = 22,9 U BR = 7,8 U BR = 22,9 U BR = 84,3 U BR = 0 ,0 U BR = 0 ,0 U BR = 0 ,0 U BR = 0 ,0 U BR = 0 ,0 U BR = 0 ,0 U BR = 0 ,0 U BR = 0 ,0 U BR = 33 ,3 U BR = 0 ,0 U BR = 0,2 U BR = 0,2 U BR = 0,2 U BR = 3,7 U BR = 7,5 U BR = 7,8 U BR = 7,8 U BR = 7,8 U BR = 2 2,9 U BR = 7,8 U BR = % Error 3,28 MHz % Error UBR= UBR= UBR= UBR= UBR= UBR= UBR= UBR= UBR= UBR= 84 42 20 13 10 6 4 3 2 1 3,69 MHz % Erro r 95 47 23 15 11 7 5 3 2 1 4 MHz 103 51 25 16 12 8 6 3 2 1 4,608 MHz % Error 119 59 29 19 14 9 7 4 3 2 0,0 0,0 0,0 0,0 0,0 0,0 6,7 0,0 6,7 2 0,0 0,4 U BR = 0,8 U BR = 1,6 U BR = 1,6 U BR = 3,1 U BR = 1,6 U BR = 6,3 U BR = 12,5 U BR = 12,5 U BR = 12,5 U BR = 0 ,0 U BR = 0 ,0 U BR = 0 ,0 U BR = 0 ,0 U BR = 0 ,0 U BR = 0 ,0 U BR = 0 ,0 U BR = 0 ,0 U BR = 0 ,0 U BR = 0 ,0 U BR = 0,2 U BR = 0,2 U BR = 0,2 U BR = 2,1 U BR = 0,2 U BR = 3,7 U BR = 7,5 U BR = 7,8 U BR = 7,8 U BR = 7,8 U BR = 7,37 MHz % Error UBR= UBR= UBR= UBR= UBR= UBR= UBR= UBR= UBR= UBR= 191 95 47 31 23 15 11 7 5 3 8 MHz % Erro r 2 07 1 03 51 34 25 16 12 8 6 3 0 ,2 0 ,2 0 ,2 0 ,8 0 ,2 2 ,1 0 ,2 3 ,7 7 ,5 7 ,8 0,0 U BR = 0,0 U BR = 0,0 U BR = 0,0 U BR = 0,0 U BR = 0,0 U BR = 0,0 U BR = 0,0 U BR = 0,0 U BR = 0,0 U BR = 77 1142E-AVR-02/03 UART Baud Rate Registers - UBRR and UBRRHI Bit $20 ($40) $09 ($29) 15 - MSB 7 14 - 13 - 12 - 11 MSB 10 9 8 LSB LSB UBRRHI UBRR 6 R R/W 0 0 5 R R/W 0 0 4 R R/W 0 0 3 R/W R/W 0 0 2 R/W R/W 0 0 1 R/W R/W 0 0 0 R/W R/W 0 0 Read/Write R R/W Initial Value 0 0 This is a 12-bit register which contains the UART Baud Rate according to the equation on the previous page. The UBRRHI contains the four most significant bits, and the UBRR contains the eight least significant bits of the UART Baud Rate. Double Speed Transmission The ATMEGA163 provides a separate UART mode which allows the user to double the communication speed. By setting the U2X bit in the UART Control and Status Register UCSRA, the UART speed will be doubled. Note, however, that the receiver will in this case only use half the number of samples (only 8 instead of 16) for data sampling and clock recovery, and therefore requires more accurate baud rate setting and system clock. The data reception will differ slightly from Normal mode. Since the speed is doubled, the Receiver front-end logic samples the signals on RXD pin at a frequency eight times the baud rate. While the line is idle, one single sample of logical zero will be interpreted as the falling edge of a start bit, and the start bit detection sequence is initiated. Let sample 1 denote the first zero-sample. Following the 1 to 0-transition, the Receiver samples the RXD pin at samples 4, 5, and 6. If two or more of these three samples are found to be logical ones, the start bit is rejected as a noise spike and the receiver starts looking for the next 1 to 0-transition. If however, a valid start bit is detected, sampling of the data bits following the start bit is performed. These bits are also sampled at samples 4, 5, and 6. The logical value found in at least two of the three samples is taken as the bit value. All bits are shifted into the Transmitter Shift Register as they are sampled. Sampling of an incoming character is shown in Figure 48. Figure 48. Sampling Received Data When the Transmission Speed is Doubled RXD START BIT RECEIVER SAMPLING D0 D1 D2 D3 D4 D5 D6 D7 STOP BIT The Baud Rate Generator in Double UART Speed Mode Note that the baud-rate equation is different from the equation on page 78 when the UART speed is doubled: f CK BAUD = ----------------------------8(UBR + 1 ) * * * * BAUD = Baud Rate fCK= Crystal Clock frequency UBR = Contents of the UBRRHI and UBRR Registers, (0 - 4095) Note that this equation is only valid when the UART Transmission Speed is doubled. For standard crystal frequencies, the most commonly used baud rates can be generated by using the UBR settings in Table 28. UBR values which yield an actual baud rate differing less than 1.5% from the target baud rate, are bold in the table. However, since the 78 ATMEGA163(L) 1142E-AVR-02/03 ATMEGA163(L) number of samples are reduced, and the system clock might have some variance (this applies especially when using resonators), it is recommended that the baud rate error is less than 0.5%. Table 28. UBR Settings at Various Crystal Frequencies in Double Speed Mode 1.0000 MHz UBR = 51 UBR = 25 UBR = 12 UBR = 8 UBR = 6 UBR = 3 UBR = 2 UBR = 1 UBR = 1 UBR = 0 3.2768 MHz UBR = 170 UBR = 84 UBR = 42 UBR = 27 UBR = 20 UBR = 13 UBR = 10 UBR = 6 UBR = 4 UBR = 3 UBR = 1 UBR = 0 7.3728 MHz UBR = 383 UBR = 191 UBR = 95 UBR = 63 UBR = 47 UBR = 31 UBR = 23 UBR = 15 UBR = 11 UBR = 7 UBR = 3 UBR = 1 UBR = 0 % Error % Error 1.8432 MHz 0.2 UBR = 95 0.2 UBR = 47 0.2 UBR = 23 3.7 UBR = 15 7.5 UBR = 11 7.8 UBR = 7 7.8 UBR = 5 7.8 UBR = 3 22.9 UBR = 2 84.3 UBR = 1 - UBR = 0 3.6864 MHz 0.2 UBR = 191 0.4 UBR = 95 0.8 UBR = 47 1.6 UBR = 31 1.6 UBR = 23 1.6 UBR = 15 3.1 UBR = 11 1.6 UBR = 7 6.2 UBR = 5 12.5 UBR = 3 12.5 UBR = 1 12.5 UBR = 0 % Error 8.0000 MHz 0.0 UBR = 416 0.0 UBR = 207 0.0 UBR = 103 0.0 UBR = 68 0.0 UBR = 51 0.0 UBR = 34 0.0 UBR = 25 0.0 UBR = 16 0.0 UBR = 12 0.0 UBR = 8 0.0 UBR = 3 0.0 UBR = 1 0.0 UBR = 0 % Error 2.0000 MHz % Error 0.2 0.2 0.2 2.1 0.2 3.7 7.5 7.8 7.8 7.8 % Error 0.2 0.2 0.2 0.8 0.2 2.1 0.2 3.7 7.5 7.8 7.8 7.8 0.0 UBR = 103 0.0 UBR = 51 0.0 UBR = 25 0.0 UBR = 16 0.0 UBR = 12 0.0 UBR = 8 0.0 UBR = 6 0.0 UBR = 3 0.0 UBR = 2 0.0 UBR = 1 0.0 % Error 4.0000 MHz 0.0 UBR = 207 0.0 UBR = 103 0.0 UBR = 51 0.0 UBR = 34 0.0 UBR = 25 0.0 UBR = 16 0.0 UBR = 12 0.0 UBR = 8 0.0 UBR = 6 0.0 UBR = 3 0.0 UBR = 1 0.0 UBR = 0 % Error 0.1 0.2 0.2 0.6 0.2 0.8 0.2 2.1 0.2 3.7 7.8 7.8 7.8 79 1142E-AVR-02/03 Two-wire Serial Interface (Byte Oriented) The Two-wire Serial Interface supports bi-directional serial communication. It is designed primarily for simple but efficient integrated circuit (IC) control. The system is comprised of two lines, SCL (Serial Clock) and SDA (Serial Data) that carry information between the ICs connected to them. Various communication configurations can be designed using this bus. Figure 49 shows a typical Two-wire Serial Bus configuration. Any device connected to the bus can be master or slave. Note that all AVR devices connected to the bus must be powered to allow any bus operation. Figure 49. Two-wire Serial Bus Configuration V CC Device 1 Device 2 Device 3 ....... Device n R1 R2 SCL SDA The Two-wire Serial Interface supports Master/Slave and Transmitter/Receiver operation at up to 217 kHz bus clock rate. The Two-wire Serial Interface has hardware support for 7-bit addressing, but is easily extended to, e.g., a 10-bit addressing format in software. When the Two-wire Serial Interface is enabled (TWEN in TWCR is set), a glitch filter is enabled for the input signals from the pins PC0 (SCL) and PC1 (SDA), and the output from these pins is slew-rate controlled. The Two-wire Serial Interface is byte oriented. The operation of the Two-wire Serial Bus is shown as a pulse diagram in Figure 50, including the START and STOP conditions and generation of ACK signal by the bus receiver. Figure 50. Two-wire Serial Bus Timing Diagram ACKNOWLEDGE FROM RECEIVER SDA MSB R/W BIT STOP CONDITION REPEATED START CONDITION 9 ACK 1 2 8 9 ACK SCL START CONDITION 1 2 7 8 The block diagram of the Two-wire Serial Interface is shown in Figure 51. 80 ATMEGA163(L) 1142E-AVR-02/03 ATMEGA163(L) Figure 51. Block Diagram of the Two-wire Serial Interface ADDRESS REGISTER AND COMPARATOR TWAR INPUT SDA OUTPUT DATA SHIFT REGISTER TWDR ACK INPUT SCL OUTPUT START/STOP AND SYNC ARBITRATION TIMING AND CONTROL SERIAL CLOCK GENERATOR STATUS CONTROL REGISTER TWCR STATE MACHINE AND STATUS DECODER STATUS REGISTER TWSR The CPU interfaces with the Two-wire Serial Interface via the following five I/O Registers: the Two-wire Serial Interface Bit Rate Register (TWBR), the Two-wire Serial Interface Control Register (TWCR), the Two-wire Serial Interface Status Register (TWSR), the Two-wire Serial Interface Data Register (TWDR), and the Two-wire Serial Interface Address Register (TWAR, used in Slave mode). AVR 8-BIT DATA BUS 81 1142E-AVR-02/03 The Two-wire Serial Interface Bit Rate Register - TWBR Bit $00 ($20) Read/Write Initial Value 7 TWBR7 R/W 0 6 TWBR6 R/W 0 5 TWBR5 R/W 0 4 TWBR4 R/W 0 3 TWBR3 R/W 0 2 TWBR2 R/W 0 1 TWBR1 R/W 0 0 TWBR0 R/W 0 TWBR * Bits 7..0 - Two-wire Serial Interface Bit Rate Register TWBR selects the division factor for the bit rate generator. The bit rate generator is a frequency divider which generates the SCL clock frequency in the Master modes according to the following equation: f CK Bit Rate = ---------------------------------------------------------16 + 2(TWBR) + t A f CK * * * * Bit Rate = SCL frequency fCK = CPU Clock frequency TWBR = Contents of the Two-wire Serial Interface Bit Rate Register tA = Bus alignment adjustion Both the Receiver and the Transmitter can stretch the low period of the SCL line when waiting for user response, thereby reducing the average bit rate. Note: TWBR should be set to a value higher than seven to ensure correct Two-wire Serial Bus functionality. The bus alignment adjustion is automatically inserted by the Two-wire Serial Interface, and ensures the validity of setup and hold times on the bus for any TWBR value higher than seven. This adjustment may vary from 200 ns to 600 ns depending on bus loads and drive capabilities of the devices connected to the bus. The Two-wire Serial Interface Control Register - TWCR Bit $36 ($56) Read/Write Initial Value 7 TWINT R/W 0 6 TWEA R/W 0 5 TWSTA R/W 0 4 TWSTO R/W 0 3 TWWC R 0 2 TWEN R/W 0 1 - R 0 0 TWIE R/W 0 TWCR * Bit 7 - TWINT: Two-wire Serial Interface Interrupt Flag This bit is set by hardware when the Two-wire Serial Interface has finished its current job and expects application software response. If the I-bit in the SREG and TWIE in the TWCR Register are set (one), the MCU will jump to the Interrupt Vector at address $22. While the TWINT Flag is set, the bus SCL clock line low period is stretched. The TWINT Flag must be cleared by software by writing a logic one to it. Note that this flag is not automaticaly cleared by hardware when executing the interrupt routine. Also note that clearing this flag starts the operation of the Two-wire Serial Interface, so all accesses to the Two-wire Serial Interface Address Register - TWAR, Two-wire Serial Interface Status Register - TWSR, and Two-wire Serial Interface Data Register - TWDR must be complete before clearing this flag. 82 ATMEGA163(L) 1142E-AVR-02/03 ATMEGA163(L) * Bit 6 - TWEA: Two-wire Serial Interface Enable Acknowledge Flag TWEA Flag controls the generation of the acknowledge pulse. If the TWEA bit is set, the ACK pulse is generated on the Two-wire Serial Bus if the following conditions are met: 1. The device's own slave address has been received. 2. A general call has been received, while the TWGCE bit in the TWAR is set. 3. A data byte has been received in Master Receiver or Slave Receiver mode. By setting the TWEA bit low, the device can be virtually disconnected from the Two-wire Serial Bus temporarily. Address recognition can then be resumed by setting the TWEA bit again. * Bit 5 - TWSTA: Two-wire Serial Bus START Condition Flag The TWSTA Flag is set by the application when it desires to become a Master on the Two-wire Serial Bus. The Two-wire Serial Interface hardware checks if the bus is available, and generates a START condition on the bus if it is free. However, if the bus is not free, the Two-wire Serial Interface waits until a STOP condition is detected, and then generates a new START condition to claim the bus Master status. * Bit 4 - TWSTO: Two-wire Serial Bus STOP Condition Flag TWSTO is a Stop Condition Flag. In Master mode setting the TWSTO bit in the Control Register will generate a STOP condition on the Two-wire Serial Bus. When the STOP condition is executed on the bus, the TWSTO bit is cleared automatically. In Slave mode setting the TWSTO bit can be used to recover from an error condition. No stop condition is generated on the bus then, but the Two-wire Serial Interface returns to a well-defined unaddressed Slave mode and releases the SCL and SDA lines to a high impedance state. * Bit 3 - TWWC: Two-wire Serial Bus Write Collision Flag The TWWC bit is set when attempting to write to the Two-wire Serial Interface Data Register - TWDR when TWINT is low. This flag is cleared by writing the TWDR Register when TWINT is high. * Bit 2 - TWEN: Two-wire Serial Interface Enable Bit The TWEN bit enables Two-wire Serial Interface operation. If this bit is cleared (zero), the bus outputs SDA and SCL are set to high impedance state, and the input signals are ignored. The interface is activated by setting this bit (one). * Bit 1 - Res: Reserved Bit This bit is a reserved bit in the ATMEGA163 and will always read as zero. 83 1142E-AVR-02/03 * Bit 0 - TWIE: Two-wire Serial Interface Interrupt Enable When this bit is enabled, and the I-bit in SREG is set, the Two-wire Serial Interface interrupt will be activated for as long as the TWINT Flag is high. The TWCR is used to control the operation of the Two-wire Serial Interface. It is used to enable the Two-wire Serial Interface, to initiate a Master access by applying a START condition to the bus, to generate a receiver acknowledge, to generate a stop condition, and to control halting of the bus while the data to be written to the bus are written to the TWDR. It also indicates a write collision if data is attempted written to TWDR while the register is inaccessible. The Two-wire Serial Interface Status Register - TWSR Bit $01 ($21) Read/Write Initial Value 7 TWS7 R 1 6 TWS6 R 1 5 TWS5 R 1 4 TWS4 R 1 3 TWS3 R 1 2 - R 0 1 - R 0 0 - R 0 TWSR * Bits 7..3 - TWS: Two-wire Serial Interface Status These five bits reflect the status of the Two-wire Serial Interface logic and the Two-wire Serial Bus. * Bits 2..0 - Res: Reserved bits These bits are reserved in ATMEGA163 and will always read as zero The TWSR is read only. It contains a status code which reflects the status of the Twowire Serial Interface logic and the Two-wire Serial Bus. There are 26 possible status codes. When TWSR contains $F8, no relevant state information is available and no Two-wire Serial Interface interrupt is requested. A valid status code is available in TWSR one CPU clock cycle after the Two-wire Serial Interface Interrupt Flag (TWINT) is set by hardware and is valid until one CPU clock cycle after TWINT is cleared by software. Table 32 to Table 36 give the status information for the various modes. The Two-wire Serial Interface Data Register - TWDR Bit $03 ($23) Read/Write Initial Value 7 TWD7 R/W 1 6 TWD6 R/W 1 5 TWD5 R/W 1 4 TWD4 R/W 1 3 TWD3 R/W 1 2 TWD2 R/W 1 1 TWD1 R/W 1 0 TWD0 R/W 1 TWDR * Bits 7..0 - TWD: Two-wire Serial Interface Data Register These eight bits constitute the next data byte to be transmitted, or the latest data byte received on the Two-wire Serial Bus. In Transmit mode, TWDR contains the next byte to be transmitted. In Receive mode, the TWDR contains the last byte received. It is writeable while the Two-wire Serial Interface is not in the process of shifting a byte. This occurs when the Two-wire Serial Interface Interrupt Flag (TWINT) is set by hardware. Note that the Data Register cannot be initialized by the user before the first interrupt occurs. The data in TWDR remain stable as long as TWINT is set. While data is shifted out, data on the bus is simultaneously shifted in. TWDR always contains the last byte present on the bus, except after a wake up from ADC Noise Reduction mode, Power-down mode, or Power-save mode by the Two-wire Serial Interface interrupt. For example, in the case of a lost bus arbitration, no data is lost in the transition from Master to Slave. Handling of the ACK Flag is controlled automatically by the Two-wire Serial Interface logic, the CPU cannot access the ACK bit directly. 84 ATMEGA163(L) 1142E-AVR-02/03 ATMEGA163(L) The Two-wire Serial Interface (Slave) Address Register - TWAR Bit $02 ($22) Read/Write Initial Value 7 TWA6 R/W 1 6 TWA5 R/W 1 5 TWA4 R/W 1 4 TWA3 R/W 1 3 TWA2 R/W 1 2 TWA1 R/W 1 1 TWA0 R/W 1 0 TWGCE R/W 0 TWAR * Bits 7..1 - TWA: Two-wire Serial Interface (Slave) Address Register These seven bits constitute the slave address of the Two-wire Serial Bus unit. * Bit 0 - TWGCE: Two-wire Serial Interface General Call Recognition Enable Bit This bit enables, if set, the recognition of the General Call given over the Two-wire Serial Bus. The TWAR should be loaded with the 7-bit slave address (in the seven most significant bits of TWAR) to which the Two-wire Serial Interface will respond when programmed as a Slave Transmitter or Receiver, and not needed in the Master modes. The LSB of TWAR is used to enable recognition of the general call address ($00). There is an associated address comparator that looks for the slave address (or generall call address if enabled) in the received serial address. If a match is found, an interrupt request is generated. Two-wire Serial Interface Modes The Two-wire Serial Interface can operate in four different modes: * * * * Master Transmitter Master Receiver Slave Receiver Slave Transmitter Data transfer in each mode of operation is shown in Figure 52 to Figure 55. These figures contain the following abbreviations: S: START condition R: Read bit (high level at SDA) W: Write bit (low level at SDA) A: Acknowledge bit (low level at SDA) A: Not acknowledge bit (high level at SDA) Data: 8-bit data byte P: STOP condition SLA: Slave Address In Figure 52 to Figure 55, circles are used to indicate that the Two-wire Serial Interface Interrupt Flag is set. The numbers in the circles show the status code held in TWSR. At these points, actions must be taken by the application to continue or complete the Twowire Serial Bus transfer. The Two-wire Serial Bus transfer is suspended until the Twowire Serial Interface Interrupt Flag is cleared by software. The Two-wire Serial Interface Interrupt Flag is not automatically cleared by hardware when executing the interrupt routine. Software has to clear the flag to continue the Twowire transfer. Also note that the Two-wire Serial Interface starts execution as soon as this bit is cleared, so that all access to TWAR, TWDR, and TWSR must have been completed before clearing this flag. 85 1142E-AVR-02/03 When the Two-wire Serial Interface Interrupt Flag is set, the status code in TWSR is used to determine the appropriate software action. For each status code, the required software action and details of the following serial transfer are given in Table 32 to Table 36. Master Transmitter Mode In the Master Transmitter mode, a number of data bytes are transmitted to a Slave Receiver (see Figure 52). Before Master Transmitter mode can be entered, the TWCR must be initialized as follows: Table 29. TWCR: Master Transmitter Mode Initialization TWCR Value TWINT 0 TWEA X TWSTA 0 TWSTO 0 TWWC 0 TWEN 1 - 0 TWIE X TWEN must be set to enable the Two-wire Serial Interface, TWSTA and TWSTO must be cleared. The Master Transmitter mode may now be entered by setting the TWSTA bit. The Twowire Serial Interface logic will then test the Two-wire Serial Bus and generate a START condition as soon as the bus becomes free. When a START condition is transmitted, the Two-wire Serial Interface Interrupt Flag (TWINT) is set by hardware, and the status code in TWSR will be $08. TWDR must then be loaded with the slave address and the data direction bit (SLA+W). Clearing the TWINT bit in software will continue the transfer. The TWINT Flag is cleared by writing a logic one to the flag. When the slave address and the direction bit have been transmitted and an acknowledgement bit has been received, TWINT is set again and a number of status codes in TWSR are possible. Possible status codes in Master mode are $18, $20, or $38. The appropriate action to be taken for each of these status codes is detailed in Table 32. The data must be loaded when TWINT is high only. If not, the access will be discarded, and the Write Collision bit - TWWC will be set in the TWCR Register. This scheme is repeated until the last byte is sent and the transfer is ended by generating a STOP condition or a repeated START condition. A STOP condition is generated by setting TWSTO, a repeated START condition is generated by setting TWSTA and TWSTO. After a repeated START condition (state $10) the Two-wire Serial Interface can access the same Slave again, or a new Slave without transmitting a STOP condition. Repeated START enables the Master to switch between Slaves, Master Transmitter mode and Master Receiver mode without loosing control over the bus. Assembly code illustrating operation of the Master Transmitter mode is given at the end of the TWI section. Master Receiver Mode In the Master Receiver mode, a number of data bytes are received from a Slave Transmitter (see Figure 53). The transfer is initialized as in the Master Transmitter mode. When the START condition has been transmitted, the TWINT Flag is set by hardware. The software must then load TWDR with the 7-bit slave address and the Data Direction bit (SLA+R). The transfer will then continue when the TWINT Flag is cleared by software. When the slave address and the direction bit have been transmitted and an acknowledgement bit has been received, TWINT is set again and a number of status codes in TWSR are possible. Possible status codes in Master mode are $40, $48, or $38. The appropriate action to be taken for each of these status codes is detailed in Table 52. Received data can be read from the TWDR Register when the TWINT Flag is set high by hardware. This scheme is repeated until the last byte has been received and a STOP condition is transmitted by writing a logic one to the TWSTO bit in the TWCR Register. 86 ATMEGA163(L) 1142E-AVR-02/03 ATMEGA163(L) After a repeated START condition (state $10), the Two-wire Serial Interface may switch to the Master Transmitter mode by loading TWDR with SLA+W or access a new Slave as Master Receiver or Transmitter. Assembly code illustrating operation of the Master Receiver mode is given at the end of the TWI section. Slave Receiver Mode In the Slave Receiver mode, a number of data bytes are received from a Master Transmitter (see Figure 54). To initiate the Slave Receiver mode, TWAR and TWCR must be initialized as follows: Table 30. TWAR: Slave Receiver Mode Initialization TWAR Value TWA6 TWA5 TWA4 TWA3 TWA2 TWA1 TWA0 TWGCE Device's Own Slave Address The upper seven bits are the address to which the Two-wire Serial Interface will respond when addressed by a Master. If the LSB is set, the Two-wire Serial Interface will respond to the general call address ($00), otherwise it will ignore the general call address. Table 31. WCR: Slave Receiver Mode Initialization TWCR Value TWINT 0 TWEA 1 TWSTA 0 TWSTO 0 TWWC 0 TWEN 1 - 0 TWIE X TWEN must be set to enable the Two-wire Serial Interface. The TWEA bit must be set to enable the acknowledgement of the device's own slave address or the general call address. TWSTA and TWSTO must be cleared. When TWAR and TWCR have been initialized, the Two-wire Serial Interface waits until it is addressed by its own slave address (or the general call address if enabled) followed by the Data Direction bit which must be "0" (write) for the Two-wire Serial Interface to operate in the Slave Receiver mode. After its own slave address and the write bit have been received, the Two-wire Serial Interface Interrupt Flag is set and a valid status code can be read from TWSR. The status code is used to determine the appropriate software action. The appropriate action to be taken for each status code is detailed in Table 34. The Slave Receiver mode may also be entered if arbitration is lost while the Two-wire Serial Interface is in the Master mode (see states $68 and $78). If the TWEA bit is reset during a transfer, the Two-wire Serial Interface will return a "Not Acknowledge" ("1") to SDA after the next received data byte. While TWEA is Reset, the Two-wire Serial Interface does not respond to its own slave address. However, the Twowire Serial Bus is still monitored and address recognition may resume at any time by setting TWEA. This implies that the TWEA bit may be used to temporarily isolate the Two-wire Serial Interface from the Two-wire Serial Bus. In ADC Noise Reduction mode, Power-down mode, and Power-save mode, the clock system to the Two-wire Serial Interface is turned off. If the Slave Receive mode is enabled, the interface can still acknowledge a general call and its own slave address by using the Two-wire Serial Bus clock as a clock source. The part will then wake-up from sleep and the Two-wire Serial Interface will hold the SCL clock wil low during the wakeup and until the TWINT Flag is cleared. Note that the Two-wire Serial Interface Data Register - TWDR - does not reflect the last byte present on the bus when waking up from these sleep modes. Assembly code illustrating operation of the Slave Receiver mode is given at the end of the TWI section. 87 1142E-AVR-02/03 Slave Transmitter Mode In the Slave Transmitter mode, a number of data bytes are transmitted to a Master Receiver (see Figure 55). The transfer is initialized as in the Slave Receiver mode. When TWAR and TWCR have been initialized, the Two-wire Serial Interface waits until it is addressed by its own slave address (or the general call address if enabled) followed by the Data Direction bit which must be "1" (read) for the Two-wire Serial Interface to operate in the Slave Transmitter mode. After its own slave address and the read bit have been received, the Two-wire Serial Interface Interrupt Flag is set and a valid status code can be read from TWSR. The status code is used to determine the appropriate software action. The appropriate action to be taken for each status code is detailed in Table 35. The slave transmitter mode may also be entered if arbitration is lost while the Two-wire Serial Interface is in the Master mode (see state $B0). If the TWEA bit is reset during a transfer, the Two-wire Serial Interface will transmit the last byte of the transfer and enter state $C0 or state $C8. the Two-wire Serial Interface is switched to the not addressed Slave mode, and will ignore the Master if it continues the transfer. Thus the Master Receiver receives all "1" as serial data. While TWEA is reset, the Two-wire Serial Interface does not respond to its own slave address. However, the Two-wire Serial Bus is still monitored and address recognition may resume at any time by setting TWEA. This implies that the TWEA bit may be used to temporarily isolate the Two-wire Serial Interface from the Two-wire Serial Bus. Assembly code illustrating operation of the Slave Receiver mode is given at the end of the TWI section. Miscellaneous States There are two status codes that do not correspond to a defined Two-wire Serial Interface state, see Table 36. Status $F8 indicates that no relevant information is available because the Two-wire Serial Interface Interrupt Flag (TWINT) is not set yet. This occurs between other states, and when the Two-wire Serial Interface is not involved in a serial transfer. Status $00 indicates that a bus error has occured during a Two-wire Serial Bus transfer. A bus error occurs when a START or STOP condition occurs at an illegal position in the format frame. Examples of such illegal positions are during the serial transfer of an address byte, a data byte or an acknowledge bit. When a bus error occurs, TWINT is set. To recover from a bus error, the TWSTO Flag must set and TWINT must be cleared by writing a logic one to it. This causes the Two-wire Serial Interface to enter the not addressed Slave mode and to clear the TWSTO Flag (no other bits in TWCR are affected). The SDA and SCL lines are released and no STOP condition is transmitted. 88 ATMEGA163(L) 1142E-AVR-02/03 ATMEGA163(L) Table 32. Status Codes for Master Transmitter Mode Application Software Response Status Code (TWSR) $08 $10 Status of the Two-wire Serial Bus and Two-wire Serial Interface Hardware A START condition has been transmitted A repeated START condition has been transmitted To TWCR To/from TWDR Load SLA+W Load SLA+W or Load SLA+R $18 SLA+W has been transmitted; ACK has been received Load data byte or No TWDR action or No TWDR action or No TWDR action $20 SLA+W has been transmitted; NOT ACK has been received Load data byte or No TWDR action or No TWDR action or No TWDR action $28 Data byte has been transmitted; ACK has been received Load data byte or No TWDR action or No TWDR action or No TWDR action $30 Data byte has been transmitted; NOT ACK has been received Load data byte or No TWDR action or No TWDR action or No TWDR action $38 Arbitration lost in SLA+W or data bytes No TWDR action or No TWDR action STA X X X 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 STO 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 TWINT 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 TWEA X X X X X X X X X X X X X X X X X X X X X Next Action Taken by Two-wire Serial Interface Hardware SLA+W will be transmitted; ACK or NOT ACK will be received SLA+W will be transmitted; ACK or NOT ACK will be received SLA+R will be transmitted; Logic will switch to Master Receiver mode Data byte will be transmitted and ACK or NOT ACK will be received Repeated START will be transmitted STOP condition will be transmitted and TWSTO Flag will be Reset STOP condition followed by a START condition will be transmitted and TWSTO Flag will be reset Data byte will be transmitted and ACK or NOT ACK will be received Repeated START will be transmitted STOP condition will be transmitted and TWSTO Flag will be Reset STOP condition followed by a START condition will be transmitted and TWSTO Flag will be Reset Data byte will be transmitted and ACK or NOT ACK will be received Repeated START will be transmitted STOP condition will be transmitted and TWSTO Flag will be Reset STOP condition followed by a START condition will be transmitted and TWSTO Flag will be Reset Data byte will be transmitted and ACK or NOT ACK will be received Repeated START will be transmitted STOP condition will be transmitted and TWSTO Flag will be Reset STOP condition followed by a START condition will be transmitted and TWSTO Flag will be Reset Two-wire Serial Bus will be released and not addressed Slave mode entered A START condition will be transmitted when the bus becomes free 89 1142E-AVR-02/03 Figure 52. Formats and States in the Master Transmitter Mode MT Successfull Transmission to a Slave Receiver S SLA W A DATA A P $08 Next Transfer Started with a Repeated Start Condition $18 $28 S SLA W $10 Not Acknowledge Received After the Slave Address A P R $20 MR Not Acknowledge Received After a Data Byte A P $30 Arbitration Lost in Slave Address or Data Byte A or A Other Master Continues A or A Other Master Continues $38 Arbitration Lost and Addressed as Slave $38 Other Master Continues A $68 $78 $B0 To Corresponding States in Slave Mode From Master to Slave DATA A Any Number of Data Bytes and their Associated Acknowledge Bits This Number (Contained in TWSR) Corresponds to a Defined State of the Two-wire Serial Bus From Slave to Master n Assembly Code Example - Master Transmitter Mode ;The Slave being addressed has address 0x64. The code examples also assumes some sort of error handling routine named ERROR. ;Part specific include file and TWI include file must be included. ; ldi out wait1: in r16, (1< ; Check value of TWI Status Register. ; If status different from START go to ERROR 90 ATMEGA163(L) 1142E-AVR-02/03 ATMEGA163(L) brne ERROR ldi out ldi out address wait2:in sbrs rjmp r16, 0xc8 TWDR, r16 ; Load SLA+W into TWDR Register r16, (1< ; Wait for TWINT Flag set. This indicates that ; been received r16, TWINT ; SLA+W has been transmitted, and ACK/NACK has in cpi brne ldi out ldi out wait3:in sbrs rjmp in cpi brne r16, TWSR ERROR r16, 0x33 TWDR, r16 ; Check value of TWI Status Register. If status r16, MT_SLA_ACK; different from MT_SLA_ACK, go to ERROR ; Load data (here, data = 0x33) into TWDR Register r16, (1< ldi out ldi out r16, 0x44 ; Load data (here, data = 0x44) into TWDR Register TWDR, r16 r16, (1< wait4:in sbrs rjmp in cpi brne ldi out r16, TWCR ; Wait for TWINT flag set. This indicates that r16, TWINT; data has been transmitted, and ACK/NACK has wait4 ; been received r16, TWSR ; Check value of TWI Status Register. If status r16, MT_DATA_ACK; different from MT_DATA_ACK, go to ERROR ERROR r16, (1< 1142E-AVR-02/03 Table 33. Status Codes for Master Receiver Mode Application Software Response Status Code (TWSR) $08 $10 Status of the Two-wire Serial Bus and Two-wire Serial Interface hardware A START condition has been transmitted A repeated START condition has been transmitted To TWCR To/from TWDR Load SLA+R Load SLA+R or Load SLA+W $38 Arbitration lost in SLA+R or NOT ACK bit No TWDR action or No TWDR actio $40 SLA+R has been transmitted; ACK has been received SLA+R has been transmitted; NOT ACK has been received No TWDR action or No TWDR action $48 No TWDR action or No TWDR action or No TWDR action $50 Data byte has been received; ACK has been returned Data byte has been received; NOT ACK has been returned Read data byte or Read data byte $58 Read data byte or Read data byte or Read data byte STA X X X 0 1 0 0 1 0 1 0 0 1 0 1 STO 0 0 0 0 0 0 0 0 1 1 0 0 0 1 1 TWINT 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 TWEA X X X X X 0 1 X X X 0 1 X X X Next Action Taken by Two-wire Serial Interface Hardware SLA+R will be transmitted ACK or NOT ACK will be received SLA+R will be transmitted ACK or NOT ACK will be received SLA+W will be transmitted Logic will switch to Master Transmitter mode. Two-wire Serial Bus will be released and not addressed Slave mode will be entered A START condition will be transmitted when the bus becomes free Data byte will be received and NOT ACK will be returned Data byte will be received and ACK will be returned Repeated START will be transmitted STOP condition will be transmitted and TWSTO Flag will be Reset STOP condition followed by a START condition will be transmitted and TWSTO Flag will be Reset Data byte will be received and NOT ACK will be returned Data byte will be received and ACK will be returned Repeated START will be transmitted STOP condition will be transmitted and TWSTO Flag will be Reset STOP condition followed by a START condition will be transmitted and TWSTO Flag will be Reset Figure 53. Formats and States in the Master Receiver Mode MR Successfull Reception From a Slave Receiver S SLA R A DATA A DATA A P $08 Next Transfer Started with a Repeated Start Condition $40 $50 $58 S SLA R $10 Not Acknowledge Received After the Slave Address A P W $48 MT Arbitration Lost in Slave Address or Data Byte A or A Other Master Continues A Other Master Continues $38 Arbitration Lost and Addressed as Slave $38 Other Master Continues A $68 $78 $B0 To corresponding states in slave mode From Master to Slave DATA A Any Number of Data Bytes and their Associated Acknowledge Bits This Number (Contained in TWSR) Corresponds to a Defined State of the Two-wire Serial Bus From Slave to Master n 92 ATMEGA163(L) 1142E-AVR-02/03 ATMEGA163(L) Assembly Code Example - Master Receiver Mode ;Part specific include file and TWI include file must be included. ; r16,TWCR r16, TWINT wait5 r16, TWSR r16, START ERROR r16, 0xc9 TWDR, r16 ; Wait for TWINT flag set. This indicates that ; the START condition has been transmitted ; Check value of TWI Status Register. If status ; different from START, go to ERROR ; Load SLA+R into TWDR Register r16, (1< r16,TWCR r16, TWINT wait6 r16, TWSR ; Wait for TWINT flag set. This indicates that ; SLA+R has been transmitted, and ACK/NACK has ; been received ; Check value of TWI Status Register. If status r16, MR_SLA_ACK; different from MR_SLA_ACK, go to ERROR ERROR r16, (1< r16,TWCR r16, TWINT wait7 r16, TWSR ERROR ; Wait for TWINT flag set. This indicates that ; data has been received and ACK returned ; Check value of TWI Status Register. If status r16, MR_DATA_ACK ; different from MR_DATA_ACK, go to ERROR in nop ldi out r16, TWDR ; Input received data from TWDR. ; r16, (1< 93 1142E-AVR-02/03 sbrs rjmp r16, TWINT wait8 ; data has been received and ACK returned in cpi brne in nop ldi out r16, TWSR ERROR r16, TWDR ; Check value of TWI Status Register. If status r16, MR_DATA_ACK ; different from MR_DATA_ACK, go to ERROR ; Input received data from TWDR. ; r16, (1< r16,TWCR r16, TWINT wait9 r16, TWSR ; Wait for TWINT flag set. This indicates that ; data has been received and NACK returned ; Check value of TWI Status Register. If status r16, MR_DATA_NACK ; different from MR_DATA_NACK, go to ERROR ERROR r16, TWDR ; Input received data from TWDR. ; ldi out r16, (1< ATMEGA163(L) 1142E-AVR-02/03 ATMEGA163(L) Table 34. Status Codes for Slave Receiver Mode Application Software Response Status code (TWSR) $60 Status of the Two-wire Serial Bus and Two-wire Serial Interface hardware Own SLA+W has been received; ACK has been returned Arbitration lost in SLA+R/W as master; own SLA+W has been received; ACK has been returned General call address has been received; ACK has been returned Arbitration lost in SLA+R/W as master; General call address has been received; ACK has been returned Previously addressed with own SLA+W; data has been received; ACK has been returned Previously addressed with own SLA+W; data has been received; NOT ACK has been returned To TWCR To/from TWDR No TWDR action or No TWDR action $68 No TWDR action or No TWDR action No TWDR action or No TWDR action $78 No TWDR action or No TWDR action Read data byte or Read data byte Read data byte or Read data byte or STA X X X X X X X X X X 0 0 STO 0 0 0 0 0 0 0 0 0 0 0 0 TWINT 1 1 1 1 1 1 1 1 1 1 1 1 TWEA 0 1 0 1 0 1 0 1 0 1 0 1 Next Action Taken by Two-wire Serial Interface Hardtware Data byte will be received and NOT ACK will be returned Data byte will be received and ACK will be returned Data byte will be received and NOT ACK will be returned Data byte will be received and ACK will be returned Data byte will be received and NOT ACK will be returned Data byte will be received and ACK will be returned Data byte will be received and NOT ACK will be returned Data byte will be received and ACK will be returned Data byte will be received and NOT ACK will be returned Data byte will be received and ACK will be returned Switched to the not addressed Slave mode; no recognition of own SLA or GCA Switched to the not addressed Slave mode; own SLA will be recognized; GCA will be recognized if TWGCE = "1" Switched to the not addressed Slave mode; no recognition of own SLA or GCA; a START condition will be transmitted when the bus becomes free Switched to the not addressed Slave mode; own SLA will be recognized; GCA will be recognized if TWGCE = "1"; a START condition will be transmitted when the bus becomes free Data byte will be received and NOT ACK will be returned Data byte will be received and ACK will be returned Switched to the not addressed Slave mode; no recognition of own SLA or GCA Switched to the not addressed Slave mode; own SLA will be recognized; GCA will be recognized if TWGCE = "1" Switched to the not addressed Slave mode; no recognition of own SLA or GCA; a START condition will be transmitted when the bus becomes free Switched to the not addressed Slave mode; own SLA will be recognized; GCA will be recognized if TWGCE = "1"; a START condition will be transmitted when the bus becomes free Switched to the not addressed Slave mode; no recognition of own SLA or GCA Switched to the not addressed Slave mode; own SLA will be recognized; GCA will be recognized if TWGCE = "1" Switched to the not addressed Slave mode; no recognition of own SLA or GCA; a START condition will be transmitted when the bus becomes free Switched to the not addressed Slave mode; own SLA will be recognized; GCA will be recognized if TWGCE = "1"; a START condition will be transmitted when the bus becomes free $70 $80 $88 Read data byte or 1 0 1 0 Read data byte 1 0 1 1 $90 Previously addressed with general call; data has been received; ACK has been returned Previously addressed with general call; data has been received; NOT ACK has been returned Read data byte or Read data byte Read data byte or Read data byte or X X 0 0 0 0 0 0 1 1 1 1 0 1 0 1 $98 Read data byte or 1 0 1 0 Read data byte 1 0 1 1 $A0 A STOP condition or repeated START condition has been received while still addressed as slave Read data byte or Read data byte or 0 0 0 0 1 1 0 1 Read data byte or 1 0 1 0 Read data byte 1 0 1 1 95 1142E-AVR-02/03 Figure 54. Formats and States in the Slave Receiver Mode Reception of the Own Slave Address and One or More Data Bytes. All are Acknowledged S SLA W A DATA A DATA A P or S $60 Last Data Byte Received is not Acknowledged $80 $80 $A0 A P or S $88 Arbitration Lost as Master and Addressed as Slave A $68 Reception of the General Call Address and One or More Data Bytes General Call A DATA A DATA A P or S $70 Last Data Byte Received is not Acknowledged $90 $90 $A0 A P or S $98 Arbitration Lost as Master and Addressed as Slave by General Call A $78 From Master to Slave DATA A Any Number of Data Bytes and their Associated Acknowledge Bits This Number (Contained in TWSR) Corresponds to a Defined State of the Two-wire Serial Bus From Slave to Master n Assembly Code Example - Slave Receiver Mode ;Part specific include file and TWI include file must be included. ; ldi out r16, (1< r16, SR_SLA_ACK ; different from SR_SLA_ACK, go to ERROR ldi out r16, (1< ATMEGA163(L) 1142E-AVR-02/03 ATMEGA163(L) ; ACK should be returned after receiving first ; data byte wait12:in sbrs rjmp r16,TWCR r16, TWINT wait12 ; Wait for TWINT flag set. This indicates that ; data has been received and ACK returned in cpi brne in nop ldi out r16, TWSR ERROR r16, TWDR ; Check value of TWI Status Register. If status r16, SR_DATA_ACK ; different from SR_DATA_ACK, go to ERROR ; Input received data from TWDR. ; r16, (1< r16,TWCR r16, TWINT wait13 r16, TWSR ERROR ; Check value of TWI Status Register. If status r16, SR_DATA_NACK ; different from SR_DATA_NACK, go to ERROR in nop ldi out r16, TWDR ; Input received data from TWDR. ; r16, (1< 97 1142E-AVR-02/03 Table 35. Status Codes for Slave Transmitter Mode Application Software Response Status Code (TWSR) $A8 Status of the Two-wire Serial Bus and Two-wire Serial Interface hardware Own SLA+R has been received; ACK has been returned To TWCR To/from TWDR Load data byte or Load data byte $B0 Arbitration lost in SLA+R/W as master; own SLA+R has been received; ACK has been returned Data byte in TWDR has been transmitted; ACK has been received Data byte in TWDR has been transmitted; NOT ACK has been received Load data byte or Load data byte Load data byte or Load data byte No TWDR action or No TWDR action or STA X X X X X X 0 0 STO 0 0 0 0 0 0 0 0 TWINT 1 1 1 1 1 1 1 1 TWEA 0 1 0 1 0 1 0 1 Next Action Taken by Two-wire Serial Interface Hardware Last data byte will be transmitted and NOT ACK should be received Data byte will be transmitted and ACK should be received Last data byte will be transmitted and NOT ACK should be received Data byte will be transmitted and ACK should be received Last data byte will be transmitted and NOT ACK should be received Data byte will be transmitted and ACK should be received Switched to the not addressed Slave mode; no recognition of own SLA or GCA Switched to the not addressed Slave mode; own SLA will be recognized; GCA will be recognized if TWGCE = "1" Switched to the not addressed Slave mode; no recognition of own SLA or GCA; a START condition will be transmitted when the bus becomes free Switched to the not addressed Slave mode; own SLA will be recognized; GCA will be recognized if TWGCE = "1"; a START condition will be transmitted when the bus becomes free Switched to the not addressed Slave mode; no recognition of own SLA or GCA Switched to the not addressed Slave mode; own SLA will be recognized; GCA will be recognized if TWGCE = "1" Switched to the not addressed slave mode; no recognition of own SLA or GCA; a START condition will be transmitted when the bus becomes free Switched to the not addressed Slave mode; own SLA will be recognized; GCA will be recognized if TWGCE = "1"; a START condition will be transmitted when the bus becomes free $B8 $C0 No TWDR action or 1 0 1 0 No TWDR action 1 0 1 1 $C8 Last data byte in TWDR has been transmitted (TWEA = "0"); ACK has been received No TWDR action or No TWDR action or 0 0 0 0 1 1 0 1 No TWDR action or 1 0 1 0 No TWDR action 1 0 1 1 Figure 55. Formats and States in the Slave Transmitter Mode Reception of the Own Slave Address and One or More Data Bytes S SLA R A DATA A DATA A P or S $A8 Arbitration Lost as Master and Addressed as Slave $B8 $C0 A $B0 Last Data Byte Transmitted. Switched to not Addressed Slave (TWEA = "0") A All 1's P or S $C8 From Master to Slave DATA A Any Number of Data Bytes and their Associated Acknowledge Bits This Number (Contained in TWSR) Corresponds to a Defined State of the Two-wire Serial Bus From Slave to Master n 98 ATMEGA163(L) 1142E-AVR-02/03 ATMEGA163(L) Assembly Code Example - Slave Transmitter Mode ; Part specific include file and TWI include file must be included. ; wait14:in r16,TWCR ; Wait for TWINT flag set. This indicates that ; SLA+R has been received, and ACK/NACK has ; been returned ; Check value of TWI Status Register. If status sbrs r16, TWINT rjmp wait14 in cpi r16, TWSR r16, ST_SLA_ACK; different from ST_SLA_ACK, go to ERROR brne ERROR ldi out ldi out r16, 0x33 TWDR, r16 r16, (1< r16, ST_DATA_ACK ; different from ST_DATA_ACK, go to ERROR ldi out ldi out r16, 0x44 TWDR, r16 ; Load data (here, data = 0x44) into TWDR Register r16, (1< r16,TWCR wait16 r16, TWSR r16, TWINT ; data has been transmitted, and ACK/NACK has r16, ST_DATA_ACK ; different from ST_DATA_ACK, go to ERROR ERROR r16, 0x55 TWDR, r16 r16, (1< 1142E-AVR-02/03 ; be received after data byte Master signalling end ; of transmission) wait17:in sbrs rjmp r16,TWCR wait17 ; Wait for TWINT flag set. This indicates that ; been received r16, TWINT ; data has been transmitted, and ACK/NACK has in cpi brne ldi r16, TWSR ERROR ; Check value of TWI Status Register. If status r16, ST_LAST_DATA ; different from ST_LAST_DATA, go to ERROR r16, (1< Table 36. Status Codes for Miscellaneous States Application Software Response Status Code (TWSR) $F8 $00 Status of the Two-wire Serial Bus and Two-wire Serial Interface hardware No relevant state information available; TWINT = "0" Bus error due to an illegal START or STOP condition To/from TWDR STA No TWDR action No TWDR action 0 To TWCR STO TWINT TWEA Next Action Taken by Two-wire Serial Interface Hardware Wait or proceed current transfer X Only the internal hardware is affected, no STOP condition is sent on the bus. In all cases, the bus is released and TWSTO is cleared. No TWCR action 1 1 TWI Include File ;***** General Master staus codes ***** .equ START transmitted .equ REP_START transmitted =$08 =$10 ;START has been ;Repeated START has been ;***** Master Transmitter staus codes ***** .equ .equ .equ MT_SLA_ACK MT_SLA_NACK MT_DATA_ACK =$18 =$20 =$28 =$30 =$38 ;SLA+W has been tramsmitted and ACK received ;SLA+W has been tramsmitted and NACK received ;Data byte has been tramsmitted and ACK ;received ;Data byte has been tramsmitted and NACK ;Arbitration lost in SLA+W or data bytes .equ MT_DATA_NACK received .equ MT_ARB_LOST ;***** Master Receiver staus codes ***** .equ .equ .equ .equ .equ MR_ARB_LOST MR_SLA_ACK MR_SLA_NACK MR_DATA_ACK MR_DATA_NACK =$38 =$40 =$48 =$50 =$58 ;Arbitration lost in SLA+R or NACK bit ;SLA+R has been tramsmitted and ACK received ;SLA+R has been tramsmitted and NACK received ;Data byte has been received and ACK returned ;Data byte has been received and NACK ; tramsmitted ;***** Slave Transmitter staus codes ***** .equ .equ .equ ST_SLA_ACK =$A8 ;Own SLA+R has been received and ACK returned ST_ARB_LOST_SLA_ACK=$B0;Arbitration lost in SLA+R/W as Master. Own ; SLA+W has been received and ACK returned ST_DATA_ACK =$B8 ;Data byte has been tramsmitted and ACK ;received 100 ATMEGA163(L) 1142E-AVR-02/03 ATMEGA163(L) .equ .equ ST_DATA_NACK ST_LAST_DATA =$C0 =$C8 ;Data byte has been tramsmitted and NACK ;received ;Last byte in I2DR has been transmitted (TWEA = ;'0'), ACK has been received ;***** Slave Receiver staus codes ***** .equ .equ .equ .equ SR_SLA_ACK =$60 ;SLA+R has been received and ACK returned SR_ARB_LOST_SLA_ACK=$68;Arbitration lost in SLA+R/W as Master. Own ;SLA+R has been received and ACK returned SR_GCALL_ACK =$70 ;Generall call has been received and ACK ;returned SR_ARB_LOST_GCALL_ACK=$78;Arbitration lost in SLA+R/W as Master. ;General Call has been received and ACK ;returned SR_DATA_ACK SR_DATA_NACK =$80 =$88 ;Previously addressed with own SLA+W. Data byte ;has been received and ACK returned ;Previously addressed with own SLA+W. Data byte ;has been received and NACK returned .equ .equ .equ .equ .equ SR_GCALL_DATA_ACK=$90;Previously addressed with General Call.Data ;byte has been received and ACK returned SR_GCALL_DATA_NACK=$98;Previously addressed with General Call. Data ;byte has been received and NACK returned SR_STOP =$A0 ;A STOP condition or repeated START condition ;has been received while still addressed as a ;slave ;***** Miscellanous States ***** .equ .equ NO_INFO BUS_ERROR =$F8 =$00 ;No relevant state information; TWINT = '0' ;Bus error due to illegal START or STOP ;condition 101 1142E-AVR-02/03 The Analog Comparator The Analog Comparator compares the input values on the positive pin PB2 (AIN0) and negative pin PB3 (AIN1). When the voltage on the positive pin PB2 (AIN0) is higher than the voltage on the negative pin PB3 (AIN1), the Analog Comparator Output, ACO, is set (one). The comparator's output can be set to trigger the Timer/Counter1 Input Capture function. In addition, the comparator can trigger a separate interrupt, exclusive to the Analog Comparator. The user can select Interrupt triggering on comparator output rise, fall or toggle. A block diagram of the comparator and its surrounding logic is shown in Figure 56. Figure 56. Analog Comparator Block Diagram BANDGAP REFERENCE ACBG ACME ADEN ADC MULTIPLEXER OUTPUT 1) Note: 1. See Figure 57 on page 106. The Analog Comparator Control And Status Register - ACSR Bit $08 ($28) Read/Write Initial Value 7 ACD R/W 0 6 ACBG R/W 0 5 ACO R N/A 4 ACI R/W 0 3 ACIE R/W 0 2 ACIC R/W 0 1 ACIS1 R/W 0 0 ACIS0 R/W 0 ACSR * Bit 7 - ACD: Analog Comparator Disable When this bit is set(one), the power to the Analog Comparator is switched off. This bit can be set at any time to turn off the Analog Comparator. This will reduce power consumption in active and Idle mode. When changing the ACD bit, the Analog Comparator Interrupt must be disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt can occur when the bit is changed. * Bit 6 - ACBG: Analog Comparator Bandgap Select When this bit is set and the BOD is enabled (BODEN Fuse is programmed), a fixed bandgap voltage of nominally 1.22V replaces the positive input to the Analog Comparator. When this bit is cleared, AIN0 is applied to the positive input of the Analog Comparator. 102 ATMEGA163(L) 1142E-AVR-02/03 ATMEGA163(L) * Bit 5 - ACO: Analog Comparator Output ACO is directly connected to the comparator output. * Bit 4 - ACI: Analog Comparator Interrupt Flag This bit is set (one) when a comparator output event triggers the Interrupt mode defined by ACIS1 and ACIS0. The Analog Comparator Interrupt routine is executed if the ACIE bit is set (one) and the I-bit in SREG is set (one). ACI is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ACI is cleared by writing a logic one to the flag. * Bit 3 - ACIE: Analog Comparator Interrupt Enable When the ACIE bit is set (one) and the I-bit in the Status Register is set (one), the Analog Comparator interrupt is activated. When cleared (zero), the interrupt is disabled. * Bit 2 - ACIC: Analog Comparator Input Capture Enable When set (one), this bit enables the Input Capture function in Timer/Counter1 to be triggered by the Analog Comparator. The comparator output is in this case directly connected to the Input Capture front-end logic, making the comparator utilize the noise canceler and edge select features of the Timer/Counter1 Input Capture interrupt. When cleared (zero), no connection between the Analog Comparator and the Input Capture function is given. To make the comparator trigger the Timer/Counter1 Input Capture interrupt, the TICIE1 bit in the Timer Interrupt Mask Register (TIMSK) must be set (one). * Bits 1, 0 - ACIS1, ACIS0: Analog Comparator Interrupt Mode Select These bits determine which comparator events that trigger the Analog Comparator interrupt. The different settings are shown in Table 37. Table 37. ACIS1/ACIS0 Settings ACIS1 0 0 1 1 ACIS0 0 1 0 1 Interrupt Mode Comparator Interrupt on Output Toggle Reserved Comparator Interrupt on Falling Output Edge Comparator Interrupt on Rising Output Edge When changing the ACIS1/ACIS0 bits, The Analog Comparator Interrupt must be disabled by clearing its Interrupt Enable bit in the ACSR Register. Otherwise an interrupt can occur when the bits are changed. 103 1142E-AVR-02/03 Analog Comparator Multiplexed Input It is possible to select any of the PA7..0 (ADC7..0) pins to replace the negative input to the Analog Comparator. The ADC multiplexer is used to select this input, and consequently, the ADC must be switched off to utilize this feature. If the Analog Comparator Multiplexer Enable bit (ACME in SFIOR) is set (one) and the ADC is switched off (ADEN in ADCSR is zero), MUX2..0 in ADMUX select the input pin to replace the negative input to the Analog Comparator, as shown in Table 38. If ACME is cleared (zero) or ADEN is set (one), PB3 (AIN1) is applied to the negative input to the Analog Comparator. Table 38. Analog Comparator Multiplexed Input ACME 0 1 1 1 1 1 1 1 1 1 ADEN x 1 0 0 0 0 0 0 0 0 MUX2..0 xxx xxx 000 001 010 011 100 101 110 111 Analog Comparator Negative Input AIN1 AIN1 ADC0 ADC1 ADC2 ADC3 ADC4 ADC5 ADC6 ADC7 104 ATMEGA163(L) 1142E-AVR-02/03 ATMEGA163(L) Analog to Digital Converter Feature List * * * * * * * * * * * * * 10-bit Resolution 0.5 LSB Integral Non-linearity 2 LSB Absolute Accuracy 65 - 260 s Conversion Time Up to 15 kSPS at Maximum Resolution Up to 76 kSPS at 8-bit Resolution Eight Multiplexed Single Ended Input Channels Optional Left Adjustment for ADC Result Readout 0 - V CC ADC Input Voltage Range Selectable 2.56V ADC Reference Voltage Free Run or Single Conversion Mode Interrupt on ADC Conversion Complete Sleep Mode Noise Canceler The ATMEGA163 features a 10-bit successive approximation ADC. The ADC is connected to an 8-channel Analog Multiplexer which allows each pin of Port A to be used as input for the ADC. The ADC contains a Sample and Hold Amplifier which ensures that the input voltage to the ADC is held at a constant level during conversion. A block diagram of the ADC is shown in Figure 57. The ADC has two separate analog supply voltage pins, AVCC and AGND. AGND must be connected to GND, and the voltage on AVCC must not differ more than 0.3V from VCC. See the paragraph ADC Noise Canceling Techniques on how to connect these pins. Internal reference voltages of nominally 2.56V or AVCC are provided On-chip. The 2.56V reference may be externally decoupled at the AREF pin by a capacitor for better noise perfomance. See "Internal Voltage Reference" on page 29 for a description of the internal voltage reference. 105 1142E-AVR-02/03 Figure 57. Analog to Digital Converter Block Schematic ADC CONVERSION COMPLETE IRQ 8-BIT DATA BUS ADIF ADIE 15 ADC DATA REGISTER (ADCH/ADCL) ADPS0 0 ADC MULTIPLEXER SELECT (ADMUX) MUX4 MUX3 MUX2 MUX1 REFS1 ADLAR REFS0 MUX0 ADC CTRL. & STATUS REGISTER (ADCSR) ADPS2 ADPS1 ADEN ADSC ADFR ADIF PRESCALER MUX DECODER CHANNEL SELECTION CONVERSION LOGIC AVCC INTERNAL 2.56 V REFERENCE AREF 10-BIT DAC SAMPLE & HOLD COMPARATOR + AGND 1.22 V BANDGAP REFERENCE ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADC1 ADC0 INPUT MUX ADC MULTIPLEXER OUTPUT Operation The ADC converts an analog input voltage to a 10-bit digital value through successive approximation. The minimum value represents AGND and the maximum value represents the voltage on the AREF pin minus 1 LSB. Optionally, AVCC or an internal 2.56V reference voltage may be connected to the AREF pin by writing to the REFSn bits in the ADMUX Register. The internal voltage reference may thus be decoupled by an external capacitor at the AREF pin to improve noise immunity. The analog input channel is selected by writing to the MUX bits in ADMUX. Any of the eight ADC input pins ADC7..0, as well as AGND and a fixed bandgap voltage reference of nominally 1.22V (VBG), can be selected as single ended inputs to the ADC. The ADC can operate in two modes - Single Conversion and Free Running mode. In Single Conversion mode, each conversion will have to be initiated by the user. In Free Running mode, the ADC is constantly sampling and updating the ADC Data Register. The ADFR bit in ADCSR selects between the two available modes. The ADC is enabled by setting the ADC Enable bit, ADEN in ADCSR. Voltage reference and input channel selections will not go into effect until ADEN is set. The ADC does not 106 ATMEGA163(L) 1142E-AVR-02/03 ADC[9:0] ATMEGA163(L) consume power when ADEN is cleared, so it is recommended to switch off the ADC before entering power saving sleep modes. A conversion is started by writing a logical one to the ADC Start Conversion bit, ADSC. This bit stays high as long as the conversion is in progress and will be set to zero by hardware when the conversion is completed. If a different data channel is selected while a conversion is in progress, the ADC will finish the current conversion before performing the channel change. The ADC generates a 10-bit result, which are presented in the ADC Data Registers, ADCH and ADCL. By default, the result is presented right adjusted, but can optionally be presented left adjusted by setting the ADLAR bit in ADMUX. If the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read ADCH. Otherwise, ADCL must be read first, then ADCH, to ensure that the content of the Data Registers belongs to the same conversion. Once ADCL is read, ADC access to Data Registers is blocked. This means that if ADCL has been read, and a conversion completes before ADCH is read, neither register is updated and the result from the conversion is lost. When ADCH is read, ADC access to the ADCH and ADCL Registers is re-enabled. The ADC has its own interrupt which can be triggered when a conversion completes. When ADC access to the Data Registers is prohibited between reading of ADCH and ADCL, the interrupt will trigger even if the result is lost. Prescaling and Conversion Timing Figure 58. ADC Prescaler ADEN CK Reset 7-BIT ADC PRESCALER ADPS0 ADPS1 ADPS2 ADC CLOCK SOURCE The successive approximation circuitry requires an input clock frequency between 50 kHz and 200 kHz to achieve maximum resolution. If a lower resolution than 10 bits is required, the input clock frequency to the ADC can be higher than 200 kHz to achieve a higher sampling rate. See "ADC Characteristics" on page 114 for more details. The ADC module contains a prescaler, which divides the system clock to an acceptable ADC clock frequency. The ADPS bits in ADCSR are used to generate a proper ADC clock input frequency from any XTAL frequency above 100 kHz. The prescaler starts counting from the moment the ADC is switched on by setting the ADEN bit in ADCSR. The prescaler keeps running for as long as the ADEN bit is set, and is continuously reset when ADEN is low. CK/128 CK/16 CK/32 CK/64 CK/2 CK/4 CK/8 107 1142E-AVR-02/03 When initiating a conversion by setting the ADSC bit in ADCSR, the conversion starts at the following rising edge of the ADC clock cycle. A normal conversion takes 13 ADC clock cycles. In certain situations, the ADC needs more clock cycles to initalization and minimize offset errors. Extended conversions take 25 ADC clock cycles and occur as the first conversion after the ADC is switched on (ADEN in ADCSR is set). Additionally, when changing voltage reference, the user may improve accuracy by disregarding the first conversion result after the reference or MUX setting was changed. The actual sample-and-hold takes place 1.5 ADC clock cycles after the start of a normal conversion and 13.5 ADC clock cycles after the start of an extended conversion. When a conversion is complete, the result is written to the ADC Data Registers, and ADIF is set. In Single Conversion mode, ADSC is cleared simultaneously. The software may then set ADSC again, and a new conversion will be initated on the first rising ADC clock edge. In Free Running mode, a new conversion will be started immediately after the conversion completes, while ADSC remains high. Using Free Running mode and an ADC clock frequency of 200 kHz gives the lowest conversion time with a maximum resolution, 65 s, equivalent to 15 kSPS. For a summary of conversion times, see Table 39. Figure 59. ADC Timing Diagram, Extended Conversion (Single Conversion Mode) Extended Conversion Next Conversion Cycle Number 1 2 12 13 14 15 16 17 18 19 20 21 22 23 24 25 1 2 3 ADC Clock ADEN ADSC ADIF ADCH ADCL Sign and MSB of Result LSB of Result MUX and REFS update Sample & Hold Conversion Complete MUX and REFS Update Figure 60. ADC Timing Diagram, Single Conversion One Conversion Next Conversion Cycle Number ADC Clock ADSC ADIF ADCH ADCL 1 2 3 4 5 6 7 8 9 10 11 12 13 1 2 3 Sign and MSB of Result LSB of Result Sample & Hold MUX and REFS Update Conversion Complete MUX and REFS Update 108 ATMEGA163(L) 1142E-AVR-02/03 ATMEGA163(L) Figure 61. ADC Timing Diagram, Free Run Conversion One Conversion 11 12 13 Next Conversion 1 2 3 4 Cycle Number ADC Clock ADSC ADIF ADCH ADCL Sign and MSB of Result LSB of Result Conversion Complete Sample & Hold MUX and REFS Update Table 39. ADC Conversion Time Sample & Hold (Cycles from Start of Conversion) 13.5 1.5 Conversion Time (Cycles) 25 13 Conversion Time (s) 125 - 500 65 - 260 Condition Extended Conversion Normal Conversions ADC Noise Canceler Function The ADC features a Noise Canceler that enables conversion during ADC Noise Reduction mode (see "Sleep Modes" on page 35) to reduce noise induced from the CPU core and other I/O peripherals. If other I/O peripherals must be active during conversion, this mode works equivalently for Idle mode. To make use of this feature, the following procedure should be used: 1. Make sure that the ADC is enabled and is not busy converting. Single Conversion Mode must be selected and the ADC conversion complete interrupt must be enabled. ADEN = 1 ADSC = 0 ADFR = 0 ADIE = 1 2. Enter ADC Noise Reduction mode (or Idle mode). The ADC will start a conversion once the CPU has been halted. 3. If no other interrupts occur before the ADC conversion completes, the ADC interrupt will wake up the CPU and execute the ADC Conversion Complete interrupt routine. 109 1142E-AVR-02/03 The ADC Multiplexer Selection Register - ADMUX Bit $07 ($27) Read/Write Initial Value 7 REFS1 R/W 0 6 REFS0 R/W 0 5 ADLAR R/W 0 4 MUX4 R/W 0 3 MUX3 R/W 0 2 MUX2 R/W 0 1 MUX1 R/W 0 0 MUX0 R/W 0 ADMUX * Bit 7, 6 - REFS1..0: Reference Selection Bits These bits select the voltage reference for the ADC, as shown in Table 17. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set). The user should disregard the first conversion result after changing these bits to obtain maximum accuracy. The internal voltage reference options may not be used if an external reference voltage is being applied to the AREF pin. Table 40. Voltage Reference Selections for ADC REFS1 0 0 1 1 REFS0 0 1 0 1 Voltage Reference Selection AREF, Internal Vref turned off AVCC with external capacitor at AREF pin Reserved Internal 2.56V Voltage Reference with external capacitor at AREF pin * Bit 5 - ADLAR: ADC Left Adjust Result The ADLAR bit affects the presentation of the ADC conversion result in the ADC Data Register. If ADLAR is cleared, the result is right adjusted. If ADLAR is set, the result is left adjusted. Changing the ADLAR bit will affect the ADC Data Register immediately, regardless of any ongoing conversions. For a complete description of this bit, see "The ADC Data Register - ADCL and ADCH" on page 112. * Bits 4..0 - MUX4..MUX0: Analog Channel and Gain Selection Bits The value of these bits selects which combination of analog inputs are connected to the ADC. See Table 41 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set). Table 41. Input Channel Selections MUX4..0 00000 00001 00010 00011 00100 00101 00110 00111 Single-ended Input ADC0 ADC1 ADC2 ADC3 ADC4 ADC5 ADC6 ADC7 110 ATMEGA163(L) 1142E-AVR-02/03 ATMEGA163(L) Table 41. Input Channel Selections (Continued) MUX4..0 01000..11101 11110 11111 Single-ended Input Reserved 1.22V (VBG) 0V (AGND) The ADC Control and Status Register - ADCSR Bit $06 ($26) Read/Write Initial Value 7 ADEN R/W 0 6 ADSC R/W 0 5 ADFR R/W 0 4 ADIF R/W 0 3 ADIE R/W 0 2 ADPS2 R/W 0 1 ADPS1 R/W 0 0 ADPS0 R/W 0 ADCSR * Bit 7 - ADEN: ADC Enable Writing a logical "1" to this bit enables the ADC. By clearing this bit to zero, the ADC is turned off. Turning the ADC off while a conversion is in progress, will terminate this conversion. * Bit 6 - ADSC: ADC Start Conversion In Single Conversion mode, a logical "1" must be written to this bit to start each conversion. In Free Running mode, a logical "1" must be written to this bit to start the first conversion. The first time ADSC has been written after the ADC has been enabled, or if ADSC is written at the same time as the ADC is enabled, an extended conversion will precede the initiated conversion. This extended conversion performs initialization of the ADC. ADSC will read as one as long as a conversion is in progress. When the conversion is complete, it returns to zero. When a extended conversion precedes a real conversion, ADSC will stay high until the real conversion completes. Writing a 0 to this bit has no effect. * Bit 5 - ADFR: ADC Free Running Select When this bit is set (one) the ADC operates in Free Running mode. In this mode, the ADC samples and updates the Data Registers continuously. Clearing this bit (zero) will terminate Free Running mode. * Bit 4 - ADIF: ADC Interrupt Flag This bit is set (one) when an ADC conversion completes and the Data Registers are updated. The ADC Conversion Complete Interrupt is executed if the ADIE bit and the Ibit in SREG are set (one). ADIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ADIF is cleared by writing a logical one to the flag. Beware that if doing a Read-Modify-Write on ADCSR, a pending interrupt can be disabled. This also applies if the SBI and CBI instructions are used. * Bit 3 - ADIE: ADC Interrupt Enable When this bit is set (one) and the I-bit in SREG is set (one), the ADC Conversion Complete Interrupt is activated. 111 1142E-AVR-02/03 * Bits 2..0 - ADPS2..0: ADC Prescaler Select Bits These bits determine the division factor between the XTAL frequency and the input clock to the ADC. Table 42. ADC Prescaler Selections ADPS2 0 0 0 0 1 1 1 1 ADPS1 0 0 1 1 0 0 1 1 ADPS0 0 1 0 1 0 1 0 1 Division Factor 2 2 4 8 16 32 64 128 The ADC Data Register - ADCL and ADCH ADLAR = 0 Bit $05 ($25) $04 ($24) 15 SIGN ADC7 7 Read/Write R R Initial Value 0 0 14 - ADC6 6 R R 0 0 13 - ADC5 5 R R 0 0 12 - ADC4 4 R R 0 0 11 - ADC3 3 R R 0 0 10 - ADC2 2 R R 0 0 9 ADC9 ADC1 1 R R 0 0 8 ADC8 ADC0 0 R R 0 0 ADCH ADCL ADLAR = 1 Bit $05 ($25) $04 ($24) 15 ADC9 ADC1 7 Read/Write R R Initial Value 0 0 14 ADC8 ADC0 6 R R 0 0 13 ADC7 - 5 R R 0 0 12 ADC6 - 4 R R 0 0 11 ADC5 - 3 R R 0 0 10 ADC4 - 2 R R 0 0 9 ADC3 - 1 R R 0 0 8 ADC2 - 0 R R 0 0 ADCH ADCL When an ADC conversion is complete, the result is found in these two registers. When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read ADCH. Otherwise, ADCL must be read first, then ADCH. The ADLAR bit in ADMUX affects the way the result is read from the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result is right adjusted. * ADC9..0: ADC Conversion result These bits represent the result from the conversion. $000 represents analog ground, and $3FF represents the selected reference voltage minus one LSB. 112 ATMEGA163(L) 1142E-AVR-02/03 ATMEGA163(L) Scanning Multiple Channels Since change of analog channel always is delayed until a conversion is finished, the Free Running mode can be used to scan multiple channels without interrupting the converter. Typically, the ADC Conversion Complete interrupt will be used to perform the channel shift. However, the user should take the following fact into consideration: The interrupt triggers once the result is ready to be read. In Free Running mode, the next conversion will start immediately when the interrupt triggers. If ADMUX is changed after the interrupt triggers, the next conversion has already started, and the old setting is used. ADC Noise Canceling Techniques Digital circuitry inside and outside the ATMEGA163 generates EMI which might affect the accuracy of analog measurements. If conversion accuracy is critical, the noise level can be reduced by applying the following techniques: 1. The analog part of the ATMEGA163 and all analog components in the application should have a separate analog ground plane on the PCB. This ground plane is connected to the digital ground plane via a single point on the PCB. 2. Keep analog signal paths as short as possible. Make sure analog tracks run over the analog ground plane, and keep them well away from high-speed switching digital tracks. 3. The AVCC pin on the ATMEGA163 should be connected to the digital VCC supply voltage via an LC network as shown in Figure 62. 4. Use the ADC noise canceler function to reduce induced noise from the CPU. 5. If some Port A pins are used as digital outputs, it is essential that these do not switch while a conversion is in progress. Figure 62. ADC Power Connections Analog Ground Plane PA0 (ADC0) PA1 (ADC1) PA2 (ADC2) PA3 (ADC3) 39 GND VCC 38 37 36 35 34 33 32 31 30 29 28 27 26 PA4 (ADC4) PA5 (ADC5) PA6 (ADC6) PA7 (ADC7) AREF AGND AVCC 10 100nF ATMEGA163 PC7 (TOSC2) 113 1142E-AVR-02/03 ADC Characteristics Table 43. ADC Characteristics Symbol Parameter Resolution Absolute accuracy Absolute accuracy Absolute accuracy Integral Non-linearity Differential Non-linearity Zero Error (Offset) Conversion Time Clock Frequency AVCC VREF VINT VBG RREF VIN RAIN Notes: Analog Supply Voltage Reference Voltage Internal Voltage Reference Bandgap Voltage Reference Reference Input Resistance Input Voltage Analog Input Resistance 1. Minimum for AVCC is 2.7V. 2. Maximum for AVCC is 5.5V. Condition Single-ended Conversion VREF = 4V ADC clock = 200 kHz VREF = 4V ADC clock = 1 MHz VREF = 4V ADC clock = 2 MHz VREF > 2V VREF > 2V VREF > 2V Free Running Conversion 65 50 VCC - 0.3 2V 2.35 1.12 6 AGND 100 2.56 1.22 10 (1) Min Typ 10 1 4 16 0.5 0.5 1 Max Units Bits 2 LSB LSB LSB LSB LSB LSB 260 200 VCC + 0.3 AVCC 2.77 1.32 13 AREF (2) s kHz V V V V k V M 114 ATMEGA163(L) 1142E-AVR-02/03 ATMEGA163(L) I/O Ports All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions. The same applies for changing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as input). Port A is an 8-bit bi-directional I/O port with internal pull-ups. Three I/O memory address locations are allocated for Port A, one each for the Data Register - PORTA, $1B($3B), Data Direction Register - DDRA, $1A($3A) and the Port A Input Pins - PINA, $19($39). The Port A Input Pins address is read only, while the Data Register and the Data Direction Register are read/write. All port pins have individually selectable pull-up resistors. The PORT A output buffers can sink 20 mA and thus drive LED displays directly. When pins PA0 to PA7 are used as inputs and are externally pulled low, they will source current if the internal pull-up resistors are activated. Port A has an alternate function as analog inputs for the ADC. If some Port A pins are configured as outputs, it is essential that these do not switch when a conversion is in progress. This might corrupt the result of the conversion. During Power-down mode, the schmitt trigger of the digital input is disconnected. This allows analog signals that are close to VCC/2 to be present during powerdown without causing excessive power consumption. The Port A Data Register - PORTA Port A Bit $1B ($3B) Read/Write Initial Value 7 PORTA7 6 PORTA6 5 PORTA5 4 PORTA4 3 PORTA3 2 PORTA2 1 PORTA1 0 PORTA0 PORTA R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 The Port A Data Direction Register - DDRA Bit $1A ($3A) Read/Write Initial Value 7 DDA7 R/W 0 6 DDA6 R/W 0 5 DDA5 R/W 0 4 DDA4 R/W 0 3 DDA3 R/W 0 2 DDA2 R/W 0 1 DDA1 R/W 0 0 DDA0 R/W 0 DDRA The Port A Input Pins Address - PINA Bit $19 ($39) Read/Write Initial Value 7 PINA7 R N/A 6 PINA6 R N/A 5 PINA5 R N/A 4 PINA4 R N/A 3 PINA3 R N/A 2 PINA2 R N/A 1 PINA1 R N/A 0 PINA0 R N/A PINA The Port A Input Pins Address - PINA - is not a register, and this address enables access to the physical value on each Port A pin. When reading PORTA the PORTA Data Latch is read, and when reading PINA, the logical values present on the pins are read. PORT A as General Digital I/O All 8 bits in PORT A are equal when used as digital I/O pins. PAn, General I/O pin: The DDAn bit in the DDRA Register selects the direction of this pin, if DDAn is set (one), PAn is configured as an output pin. If DDAn is cleared (zero), PAn is configured as an input pin. If PORTAn is set (one) when the pin configured as an input pin, the MOS pull up resistor is activated. To switch the pull up resistor off, the PORTAn has to be cleared (zero), the pin has to be configured as an output pin, or the 115 1142E-AVR-02/03 PUD bit has to be set. The Port A pins are tri-stated when a reset condition becomes active, even if the clock is not running. Table 44. DDAn Effects on PORTA Pins(1) DDAn 0 0 0 1 1 Note: PORTAn 0 1 1 0 1 PUD x 1 0 x x I/O Input Input Input Output Output Pull Up No No Yes No No Comment Tri-state (Hi-Z) Tri-state (Hi-Z) PAn will source current if ext. pulled low. Push-pull Zero Output Push-pull One Output 1. n: 7,6...0, pin number. PORT A Schematics Note that all port pins are synchronized. The synchronization latches are not shown in the figure. Figure 63. PORTA Schematic Diagrams (Pins PA0 - PA7) RD MOS PULLUP PUD RESET Q D DDAn C RESET PDn Q D PORTAn C RL WP PWRDN RP TO ADC MUX WP: WD: RL: RP: RD: n: PUD: WRITE PORTA WRITE DDRA READ PORTA LATCH READ PORTA PIN READ DDRA 0-7 PULL-UP DISABLE ADCn 116 ATMEGA163(L) 1142E-AVR-02/03 DATA BUS WD ATMEGA163(L) Port B Port B is an 8-bit bi-directional I/O port with internal pull-ups. Three I/O memory address locations are allocated for Port B, one each for the Data Register - PORTB, $18($38), Data Direction Register - DDRB, $17($37) and the Port B Input Pins - PINB, $16($36). The Port B Input Pins address is read only, while the Data Register and the Data Direction Register are read/write. All port pins have individually selectable pull-up resistors. The Port B output buffers can sink 20 mA and thus drive LED displays directly. When pins PB0 to PB7 are used as inputs and are externally pulled low, they will source current if the internal pull-up resistors are activated. The Port B pins with alternate functions are shown in Table 45. Table 45. Port B Pins Alternate Functions Port Pin PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 Alternate Functions T0 (Timer/Counter0 External Counter Input) T1 (Timer/Counter1 External Counter Input) AIN0 (Analog Comparator Positive Input) AIN1 (Analog Comparator Negative Input) SS (SPI Slave Select Input) MOSI (SPI Bus Master Output/Slave Input) MISO (SPI Bus Master Input/Slave Output) SCK (SPI Bus Serial Clock) When the pins are used for the alternate function, the DDRB and PORTB Registers have to be set according to the alternate function description. The Port B Data Register - PORTB Bit $18 ($38) Read/Write Initial Value 7 PORTB7 6 PORTB6 5 PORTB5 4 PORTB4 3 PORTB3 2 PORTB2 1 PORTB1 0 PORTB0 PORTB R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 The Port B Data Direction Register - DDRB Bit $17 ($37) Read/Write Initial Value 7 DDB7 R/W 0 6 DDB6 R/W 0 5 DDB5 R/W 0 4 DDB4 R/W 0 3 DDB3 R/W 0 2 DDB2 R/W 0 1 DDB1 R/W 0 0 DDB0 R/W 0 DDRB The Port B Input Pins Address - PINB Bit $16 ($36) Read/Write Initial Value 7 PINB7 R N/A 6 PINB6 R N/A 5 PINB5 R N/A 4 PINB4 R N/A 3 PINB3 R N/A 2 PINB2 R N/A 1 PINB1 R N/A 0 PINB0 R N/A PINB The Port B Input Pins Address - PINB - is not a register, and this address enables access to the physical value on each Port B pin. When reading PORTB, the PORTB Data Latch is read, and when reading PINB, the logical values present on the pins are read. 117 1142E-AVR-02/03 Port B As General Digital I/O All eight bits in Port B are equal when used as digital I/O pins. PBn, General I/O pin: The DDBn bit in the DDRB Register selects the direction of this pin, if DDBn is set (one), PBn is configured as an output pin. If DDBn is cleared (zero), PBn is configured as an input pin. If PORTBn is set (one) when the pin configured as an input pin, the MOS pull up resistor is activated. To switch the pull up resistor off, the PORTBn has to be cleared (zero), the pin has to be configured as an output pin, or the PUD bit has to be set. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Table 46. DDBn Effects on Port B Pins(1) DDBn 0 0 0 1 1 Note: PORTBn 0 1 1 0 1 PUD x 1 0 x x I/O Input Input Input Output Output Pull Up No No Yes No No Comment Tri-state (Hi-Z) Tri-state (Hi-Z) PBn will source current if ext. pulled low. Push-pull Zero Output Push-pull One Output 1. n: 7,6...0, pin number. Alternate Functions Of PORTB The alternate pin configuration is as follows: * SCK - PORTB, Bit 7 SCK: Master Clock output, Slave Clock input pin for SPI channel. When the SPI is enabled as a Slave, this pin is configured as an input regardless of the setting of DDB7. When the SPI is enabled as a Master, the data direction of this pin is controlled by DDB7. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB7 bit. See the description of the SPI port for further details. * MISO - PORTB, Bit 6 MISO: Master Data input, Slave Data output pin for SPI channel. When the SPI is enabled as a Master, this pin is configured as an input regardless of the setting of DDB6. When the SPI is enabled as a Slave, the data direction of this pin is controlled by DDB6. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB6 bit. See the description of the SPI port for further details. * MOSI - PORTB, Bit 5 MOSI: SPI Master Data output, Slave Data input for SPI channel. When the SPI is enabled as a Slave, this pin is configured as an input regardless of the setting of DDB5. When the SPI is enabled as a Master, the data direction of this pin is controlled by DDB5. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB5 bit. See the description of the SPI port for further details. * SS - PORTB, Bit 4 SS: Slave Port Select input. When the SPI is enabled as a Slave, this pin is configured as an input regardless of the setting of DDB4. As a slave, the SPI is activated when this pin is driven low. When the SPI is enabled as a Master, the data direction of this pin is controlled by DDB4. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB4 bit. See the description of the SPI port for further details. 118 ATMEGA163(L) 1142E-AVR-02/03 ATMEGA163(L) * AIN1 - PORTB, Bit 3 AIN1, Analog Comparator Negative input. When configured as an input (DDB3 is cleared (zero)) and with the internal MOS pull up resistor switched off (PB3 is cleared (zero)), this pin also serves as the negative input of the On-chip Analog Comparator. During Power-down mode, the schmitt trigger of the digital input is disconnected. This allows analog signals which are close to VCC/2 to be present during Power-down without causing excessive power consumption. * AIN0 - PORTB, Bit 2 AIN0, Analog Comparator Positive input. When configured as an input (DDB2 is cleared (zero)) and with the internal MOS pull up resistor switched off (PB2 is cleared (zero)), this pin also serves as the positive input of the On-chip Analog Comparator. During Power-down mode, the schmitt trigger of the digital input is disconnected. This allows analog signals which are close to VCC/2 to be present during Power-down without causing excessive power consumption. * T1 - PORTB, Bit 1 T1, Timer/Counter1 Counter Source. See the Timer description for further details. * T0 - PORTB, Bit 0 T0: Timer/Counter0 Counter Source. See the Timer description for further details. Port B Schematics Note that all port pins are synchronized. The synchronization latches are not shown in the figures. Figure 64. PORTB Schematic Diagram (Pins PB0 and PB1) PUD PUD: PULL-UP DISABLE 2 119 1142E-AVR-02/03 Figure 65. PORTB Schematic Diagram (Pins PB2 and PB3) RD MOS PULLUP PUD RESET Q D DDBn C RESET PBn Q D PORTBn C RL WP PWRDN RP TO COMPARATOR WP: WD: RL: RP: RD: n: m: PUD: WRITE PORTB WRITE DDRB READ PORTB LATCH READ PORTB PIN READ DDRB 2, 3 0, 1 PULL-UP DISABLE AINm Figure 66. PORTB Schematic Diagram (Pin PB4) RD MOS PULLUP PUD RESET Q D DDB4 C RESET PB4 Q D PORTB4 C RL WP RP WP: WD: RL: RP: RD: MSTR: SPE: PUD: WRITE PORTB WRITE DDRB READ PORTB LATCH READ PORTB PIN READ DDRB SPI MASTER ENABLE SPI ENABLE PULL-UP DISABLE MSTR SPE SPI SS 120 ATMEGA163(L) 1142E-AVR-02/03 DATA BUS WD DATA BUS WD ATMEGA163(L) Figure 67. PORTB Schematic Diagram (Pin PB5) RD MOS PULLUP PUD RESET R Q D DDB5 C RESET R Q D PORTB5 C RL PB5 WP RP WP: WD: RL: RP: RD: SPE: MSTR: PUD: WRITE PORTB WRITE DDRB READ PORTB LATCH READ PORTB PIN READ DDRB SPI ENABLE MASTER SELECT PULL-UP DISABLE MSTR SPE SPI MASTER OUT SPI SLAVE IN Figure 68. PORTB Schematic Diagram (Pin PB6) RD MOS PULLUP PUD RESET R Q D DDB6 C RESET R Q D PORTB6 C RL PB6 WP RP WP: WD: RL: RP: RD: SPE: MSTR PUD: WRITE PORTB WRITE DDRB READ PORTB LATCH READ PORTB PIN READ DDRB SPI ENABLE MASTER SELECT PULL-UP DISABLE MSTR SPE SPI SLAVE OUT SPI MASTER IN DATA BUS WD DATA BUS WD 121 1142E-AVR-02/03 Figure 69. PORTB Schematic Diagram (Pin PB7) RD MOS PULLUP PUD RESET R Q D DDB7 C RESET R Q D PORTB7 C RL PB7 WP RP WP: WD: RL: RP: RD: SPE: MSTR PUD: WRITE PORTB WRITE DDRB READ PORTB LATCH READ PORTB PIN READ DDRB SPI ENABLE MASTER SELECT PULL-UP DISABLE MSTR SPE SPI ClLOCK OUT SPI CLOCK IN 122 ATMEGA163(L) 1142E-AVR-02/03 DATA BUS WD ATMEGA163(L) Port C Port C is an 8-bit bi-directional I/O port with internal pull-ups. Three I/O memory address locations are allocated for the Port C, one each for the Data Register - PORTC, $15($35), Data Direction Register - DDRC, $14($34) and the Port C Input Pins - PINC, $13($33). The Port C Input Pins address is read only, while the Data Register and the Data Direction Register are read/write. All port pins have individually selectable pull-up resistors. The PORT C output buffers can sink 20 mA and thus drive LED displays directly. When pins PC0 to PC7 are used as inputs and are externally pulled low, they will source current if the internal pull-up resistors are activated. Table 47. Port C Pins Alternate Functions Port Pin PC0 PC1 PC6 PC7 Alternate Function SCL (Two-wire Serial Bus Clock Line) SDA (Two-wire Serial Bus Data Input/Output Line) TOSC1 (Timer Oscillator Pin 1) TOSC2 (Timer Oscillator Pin 2) The Port C Data Register - PORTC Bit $15 ($35) Read/Write Initial Value 7 PORTC7 6 PORTC6 5 PORTC5 4 PORTC4 3 PORTC3 2 PORTC2 1 PORTC1 0 PORTC0 PORTC R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 The Port C Data Direction Register - DDRC Bit $14 ($34) Read/Write Initial Value 7 DDC7 R/W 0 6 DDC6 R/W 0 5 DDC5 R/W 0 4 DDC4 R/W 0 3 DDC3 R/W 0 2 DDC2 R/W 0 1 DDC1 R/W 0 0 DDC0 R/W 0 DDRC The Port C Input Pins Address - PINC Bit $13 ($33) Read/Write Initial Value 7 PINC7 R N/A 6 PINC6 R N/A 5 PINC5 R N/A 4 PINC4 R N/A 3 PINC3 R N/A 2 PINC2 R N/A 1 PINC1 R N/A 0 PINC0 R N/A PINC The Port C Input Pins Address - PINC - is not a register, and this address enables access to the physical value on each Port C pin. When reading PORTC, the PORTC Data Latch is read, and when reading PINC, the logical values present on the pins are read. Port C as General Digital I/O All eight bits in PORT C are equal when used as digital I/O pins. PCn, General I/O pin: The DDCn bit in the DDRC Register selects the direction of this pin, if DDCn is set (one), PCn is configured as an output pin. If DDCn is cleared (zero), PCn is configured as an input pin. If PORTCn is set (one) when the pin configured as an input pin, the MOS pull up resistor is activated. To switch the pull up resistor off, PORTCn has to be cleared (zero), the pin has to be configured as an output pin, or the PUD bit has to be set. The Port C pins are tri-stated when a reset condition becomes active, even if the clock is not running. 123 1142E-AVR-02/03 Table 48. DDCn Effects on PORT C Pins(1) DDCn 0 0 0 1 1 Note: PORTCn 0 1 1 0 1 PUD x 1 0 x x I/O Input Input Input Output Output Pull Up No No Yes No No Comment Tri-state (Hi-Z) Tri-state (Hi-Z) PCn will source current if ext. pulled low. Push-pull Zero Output Push-pull One Output 1. n: 7...0, pin number Alternate Functions of PORTC * TOSC2 - PORTC, Bit 7 TOSC2, Timer Oscillator pin 2: When the AS2 bit in ASSR is set (one) to enable asynchronous clocking of Timer/Counter2, pin PC7 is disconnected from the port, and becomes the inverting output of the Oscillator amplifier. In this mode, a crystal Oscillator is connected to this pin, and the pin can not be used as an I/O pin. * TOSC1 - PORTC, Bit 6 TOSC1, Timer Oscillator pin 1: When the AS2 bit in ASSR is set (one) to enable asynchronous clocking of Timer/Counter1, pin PC6 is disconnected from the port, and becomes the input of the inverting Oscillator amplifier. In this mode, a crystal Oscillator is connected to this pin, and the pin can not be used as an I/O pin. * SDA - PORTC, Bit 1 SDA, Two-wire Serial Bus Data: When the TWEN bit in TWCR is set (one) to enable the Two-wire Serial Interface, pin PC1 is disconnected from the port and becomes the Serial Data I/O pin for the Two-wire Serial Interface. In this mode, there is a spike filter on the pin to capture spikes shorter than 50 ns on the input signal, and the pin is driven by an open collector driver with slew rate limitation. * SCL - PORTC, Bit 0 SCL, Two-wire Serial Interface Clock: When the TWEN bit in TWCR is set (one) to enable the Two-wire Serial Interface, pin PC1 is disconnected from the port and becomes the Serial Clock I/O pin for the Two-wire Serial Interface. In this mode, there is a spike filter on the pin to capture spikes shorter than 50 ns on the input signal. 124 ATMEGA163(L) 1142E-AVR-02/03 ATMEGA163(L) Port C Schematics Note that all port pins are synchronized. The synchronization latches are not shown in the figure. Figure 70. PORTC Schematic Diagram (Pins PC0 - PC1) 0 DDCn PUD 1 PCn n 0 1 SCL/SDA out SCL/SDA in TWEN PUD: PULL-UP DISABLE n = 0, 1 125 1142E-AVR-02/03 Figure 71. PORTC Schematic Diagram (Pins PC2 - PC5) RD MOS PULLUP PUD RESET R Q D DDCn C RESET R Q D PORTCn C RL PCn WP RP WP: WD: RL: RP: RD: PUD: n: WRITE PORTC WRITE DDRC READ PORTC LATCH READ PORTC PIN READ DDRC PULL-UP DISABLE 2..5 Figure 72. PORTC Schematic Diagram (Pins PC6) RD MOS PULLUP PUD RESET R Q D DDC6 C RESET R Q D PORTC6 C RL PC6 WP RP 0 1 AS2 T/C2 OSC AMP INPUT WP: WD: RL: RP: RD: AS2: PUD: WRITE PORTC WRITE DDRC READ PORTC LATCH READ PORTC PIN READ DDRC ASYNCH SELECT T/C2 PULL-UP DISABLE 126 ATMEGA163(L) 1142E-AVR-02/03 DATA BUS WD DATA BUS WD ATMEGA163(L) Figure 73. PORTC Schematic Diagram (Pins PC7) PUD 0 1 PUD: PULL-UP DISABLE 127 1142E-AVR-02/03 Port D Port D is an 8 bit bi-directional I/O port with internal pull-up resistors. Three I/O memory address locations are allocated for Port D, one each for the Data Register - PORTD, $12($32), Data Direction Register - DDRD, $11($31) and the Port D Input Pins - PIND, $10($30). The Port D Input Pins address is read only, while the Data Register and the Data Direction Register are read/write. The Port D output buffers can sink 20 mA. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. Some Port D pins have alternate functions as shown in Table 49. Table 49. Port D Pins Alternate Functions Port Pin PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 Alternate Function RXD (UART Input Pin) TXD (UART Output Pin) INT0 (External Interrupt 0 Input) INT1 (External Interrupt 1 Input) OC1B (Timer/Counter1 Output CompareB Match Output) OC1A (Timer/Counter1 Output CompareA Match Output) ICP (Timer/Counter1 Input Capture Pin) OC2 (Timer/Counter2 Output Compare Match Output) The Port D Data Register - PORTD Bit $12 ($32) Read/Write Initial Value 7 PORTD7 6 PORTD6 5 PORTD5 4 PORTD4 3 PORTD3 2 PORTD2 1 PORTD1 0 PORTD0 PORTD R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 The Port D Data Direction Register - DDRD Bit $11 ($31) Read/Write Initial Value 7 DDD7 R/W 0 6 DDD6 R/W 0 5 DDD5 R/W 0 4 DDD4 R/W 0 3 DDD3 R/W 0 2 DDD2 R/W 0 1 DDD1 R/W 0 0 DDD0 R/W 0 DDRD The Port D Input Pins Address - PIND Bit $10 ($30) Read/Write Initial Value 7 PIND7 R N/A 6 PIND6 R N/A 5 PIND5 R N/A 4 PIND4 R N/A 3 PIND3 R N/A 2 PIND2 R N/A 1 PIND1 R N/A 0 PIND0 R N/A PIND The Port D Input Pins Address - PIND - is not a register, and this address enables access to the physical value on each Port D pin. When reading PORTD, the PORTD Data Latch is read, and when reading PIND, the logical values present on the pins are read. 128 ATMEGA163(L) 1142E-AVR-02/03 ATMEGA163(L) Port D as General Digital I/O PDn, General I/O pin: The DDDn bit in the DDRD Register selects the direction of this pin. If DDDn is set (one), PDn is configured as an output pin. If DDDn is cleared (zero), PDn is configured as an input pin. If PDn is set (one) when configured as an input pin the MOS pull up resistor is activated. To switch the pull up resistor off the PDn has to be cleared (zero), the pin has to be configured as an output pin, or the PUD bit has to be set. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running. Table 50. DDDn Bits on Port D Pins(1) DDDn 0 0 0 1 1 Note: PORTDn 0 1 1 0 1 PUD x 1 0 x x I/O Input Input Input Output Output Pull Up No No Yes No No Comment Tri-state (Hi-Z) Tri-state (Hi-Z) PDn will source current if ext. pulled low. Push-pull Zero Output Push-pull One Output 1. n: 7,6...0, pin number. Alternate Functions of PORTD * OC2 - PORTD, Bit 7 OC2, Timer/Counter2 Output Compare Match output: The PD7 pin can serve as an external output for the Timer/Counter2 Output Compare. The pin has to be configured as an output (DDD7 set (one)) to serve this function. See the Timer description on how to enable this function. The OC2 pin is also the output pin for the PWM mode timer function. * ICP - PORTD, Bit 6 IC P - Inp u t C ap tu re Pin : Th e PD 6 pin ca n a ct a s an In p ut Ca p tu re p in fo r Timer/Counter1. The pin has to be configured as an input (DDD6 cleared(zero)) to serve this function. See the timer description on how to enable this function. * OC1A - PORTD, Bit 5 OC1A, Output Compare Match A output: The PD5 pin can serve as an external output for the Timer/Counter1 Output Compare A. The pin has to be configured as an output (DDD5 set (one)) to serve this function. See the timer description on how to enable this function. The OC1A pin is also the output pin for the PWM mode timer function. * OC1B - PORTD, Bit 4 OC1B, Output Compare Match B output: The PD4 pin can serve as an external output for the Timer/Counter1 Output Compare B. The pin has to be configured as an output (DDD4 set (one)) to serve this function. See the timer description on how to enable this function. The OC1B pin is also the output pin for the PWM mode timer function. * INT1 - PORTD, Bit 3 INT1, External Interrupt Source 1: The PD3 pin can serve as an External Interrupt Source to the MCU. See the interrupt description for further details, and how to enable the source. 129 1142E-AVR-02/03 * INT0 - PORTD, Bit 2 INT0, External Interrupt Source 0: The PD2 pin can serve as an External Interrupt Source to the MCU. See the interrupt description for further details, and how to enable the source. * TXD - Port D, Bit 1 TXD, Transmit Data (Data output pin for the UART). When the UART Transmitter is enabled, this pin is configured as an output regardless of the value of DDRD1. * RXD - Port D, Bit 0 RXD, Receive Data (Data input pin for the UART). When the UART Receiver is enabled this pin is configured as an input regardless of the value of DDRD0. When the UART forces this pin to be an input, a logical one in PORTD0 will turn on the internal pull-up. Port D Schematics Note that all port pins are synchronized. The synchronization latches are not shown in the figures. Figure 74. PORTD Schematic Diagram (Pin PD0) RD MOS PULLUP PUD RESET Q D DDD0 C RESET PD0 Q D PORTD0 C RL WP RP WP: WD: RL: RP: RD: RXD: RXEN: PUD: WRITE PORTD WRITE DDRD READ PORTD LATCH READ PORTD PIN READ DDRD UART RECEIVE DATA UART RECEIVE ENABLE PULL-UP DISABLE RXEN RXD 130 ATMEGA163(L) 1142E-AVR-02/03 DATA BUS WD ATMEGA163(L) Figure 75. PORTD Schematic Diagram (Pin PD1) RD MOS PULLUP PUD RESET R Q D DDD1 C RESET R Q D PORTD1 C RL PD1 WP RP WP: WD: RL: RP: RD: TXD: TXEN: PUD: WRITE PORTD WRITE DDRD READ PORTD LATCH READ PORTD PIN READ DDRD UART TRANSMIT DATA UART TRANSMIT ENABLE PULL-UP DISABLE TXEN TXD Figure 76. PORTD Schematic Diagram (Pins PD2 and PD3) PUD PUD: PULL-UP DISABLE n: 2, 3 m: 0, 1 DATA BUS WD 131 1142E-AVR-02/03 Figure 77. PORTD Schematic Diagram (Pins PD4 and PD5) PUD PUD: PULL-UP DISABLE Figure 78. PORTD Schematic Diagram (Pin PD6) RD MOS PULLUP PUD RESET R Q D DDD6 C RESET R Q D PORTD6 C RL PD6 WP RP WP: WD: RL: RP: RD: ACIC: ACO: PUD: WRITE PORTD WRITE DDRD READ PORTD LATCH READ PORTD PIN READ DDRD COMPARATOR IC ENABLE COMPARATOR OUTPUT PULL-UP DISABLE 0 NOISE CANCELER 1 ICNC1 ICES1 ACIC ACO EDGE SELECT ICF1 132 ATMEGA163(L) 1142E-AVR-02/03 DATA BUS WD ATMEGA163(L) Figure 79. PORTD Schematic Diagram (Pin PD7) PUD PUD: PULL-UP DISABLE 133 1142E-AVR-02/03 Memory Programming Boot Loader Support The ATMEGA163 provides a mechanism for Programming and Re-programming code by the MCU itself. This feature allows flexible application software updates, controlled by the MCU using a Flash-resident Boot Loader program. This makes it possible to program the AVR in a target system without access to its SPI pins. The Boot Loader program can use any available data interface and associated protocol, such as UART serial bus interface, to input or output program code, and write (program) that code into the Flash memory, or read the code from the Flash memory. The ATMEGA163 Flash memory is organized in two main sections: * * The Application Flash section The Boot Loader Flash section The Application Flash section and the Boot Loader Flash section have seperate Boot Lock bits. Thus the user can select different levels of protection for the two sections. The Store Program Memory (SPM) instruction can only be executed from the Boot Loader Flash section. The Program Flash memory in ATMEGA163 is divided into 128 pages of 64 words each. The Boot Loader Flash section is located at the high address space of the Flash, and can be configured through the BOOTSZ Fuses as shown in Table 51. Table 51. Boot Size Configuration BOOTSZ1 BOOTSZ0 Boot Size 128 Words 256 Words 512 Words 1024 Words Pages 2 4 8 16 Application Flash Addresses $0000 - $1F7F $0000 - $1EFF $0000 - $1DFF $0000 - $1BFF Boot Flash Addresses $1F80 - $1FFF $1F00 - $1FFF $1E00 - $1FFF $1C00 - $1FFF 1 1 0 0 1 0 1 0 134 ATMEGA163(L) 1142E-AVR-02/03 ATMEGA163(L) Figure 80. Memory Sections Pages Program Memory BOOTSZ = '11' $0000 Pages Program Memory BOOTSZ = '10' $0000 126 Application Flash Section (8064 x 16) 124 Application Flash Section (7936 x 16) 2 Boot Flash Section (128 x 16) $1F7F $1F80 $1FFF 4 Boot Flash Section (256 x 16) $1EFF $1F00 $1FFF Pages Program Memory BOOTSZ = '01' $0000 Pages Program Memory BOOTSZ = '00' $0000 120 Application Flash Section (7680 x 16) 112 Application Flash Section (7168 x 16) $1DFF $1E00 8 $1BFF $1C00 16 Boot Flash Section (512 x 16) $1FFF Boot Flash Section (1024 x 16) $1FFF 135 1142E-AVR-02/03 Entering the Boot Loader Program The SPM instruction can access the entire Flash, but can only be executed from the Boot Loader Flash section. If no Boot Loader capability is needed, the entire Flash is available for application code. Entering the Boot Loader takes place by a jump or call from the application program. This may be initiated by some trigger such as a command received via UART or SPI interface, for example. Alternatively, the Boot Reset Fuse can be programmed so that the Reset Vector is pointing to the Boot Flash start address after a reset. In this case, the Boot Loader is started after a reset. After the application code is loaded, the program can start executing the application code. Note that the fuses cannot be changed by the MCU itself. This means that once the Boot Reset Fuse is programmed, the Reset Vector will always point to the Boot Loader Reset and the fuse can only be changed through the serial or parallel programming interface. Table 52. Boot Reset Fuse BOOTRST 1 0 Reset Address Reset Vector = Application Reset (address $0000) Reset Vector = Boot Loader Reset (see Table 51) Capabilities of the Boot Loader The program code within the Boot Loader section has the capability to read from and write into the entire Flash, including the Boot Loader memory. This allows the user to update both the Application code and the Boot Loader code that handles the software update. The Boot Loader can thus even modify itself, and it can also erase itself from the code if the feature is not needed anymore. Programming of the Flash is executed one page at a time. The Flash page must be erased first for correct programming. The general Write Lock (Lock bit 2) does not control the programming of the Flash memory by SPM instruction. Similarly, the general Read/Write Lock (Lock bit 1) does not control reading nor writing by LPM/SPM, if it is attempted. The Program memory can only be updated page by page, not word by word. One page is 128 bytes (64 words). The Program memory will be modified by first performing Page Erase, then filling the temporary page buffer one word at a time using SPM, and then executing Page Write. If only part of the page needs to be changed, the other parts must be stored (for example in internal SRAM) before the erase, and then be rewritten. The temporary page buffer can be accessed in a random sequence. It is essential that the page address used in both the Page Erase and Page Write operation is addressing the same page. See "Assembly code example for a Boot Loader" on page 141 for an assembly code example. Se e Table 60 on p age 156 for typical p rogr amming times w hen usin g SelfProgramming. Self-Programming the Flash Performing Page Erase by SPM To execute Page Erase, set up the address in the Z-pointer, write "00011" to the five LSB in SPMCR and execute SPM within four clock cycles after writing SPMCR. The data in R1 and R0 is ignored. The page address must be written to Z13:Z7. Other bits in the Z-pointer will be ignored during this operation. It is recommended that the interrupts are disabled during the page erase operation. To write an instruction word, set up the address in the Z-pointer and data in R1:R0, write "00001" to the five LSB in SPMCR and execute SPM within four clock cycles after writing SPMCR. The content of Z6:Z1 is used to address the data in the temporary buffer. Z13:Z7 must point to the page that is supposed to be written. Fill the Temporary Buffer (Page Load) 136 ATMEGA163(L) 1142E-AVR-02/03 ATMEGA163(L) Perform a Page Write To execute Page Write, set up the address in the Z-pointer, write "00101" to the five LSB in SPMCR and execute SPM within four clock cycles after writing SPMCR. The data in R1 and R0 is ignored. The page address must be written to Z13:Z7. During this operation, Z6:Z0 must be zero to ensure that the page is written correctly. It is recommended that the interrupts are disabled during the page write operation. Special care must be taken if the user allows the Boot Loader section to be updated by leaving Boot Lock bit 11 unprogrammed. An accidental write to the Boot Loader itself can corrupt the entire Boot Loader, and further software updates might be impossible. If it is not necessary to change the Boot Loader software itself, it is recommended to program the Boot Lock Bit 11 to protect the Boot Loader software from any internal software changes. Though the CPU is halted during Page Write, Page Erase or Lock bit write, for future compatibility, the user software must poll for SPM complete by reading the SPMCR Register and loop until the SPMEN bit is cleared after a programming operation. See "Assembly code example for a Boot Loader" on page 141 for a code example. To ensure proper instruction pipelining after programming action (Page Erase, Page Write, or Lock bit write), the SPM instruction must be followed with the sequence (.dw $FFFF - NOP) as shown below: spm .dw $FFFF nop Consideration while Updating the Boot Loader Section Wait for SPM Instruction to Complete Instruction Word Read after Page Erase, Page Write, and Lock Bit Write If not, the instruction following SPM might fail. It is not necessary to add this sequence when the SPM instruction only loads the temporary buffer. Avoid Reading the Application Section During SelfProgramming During Self-Programming (either Page Erase or Page Write), the user software should not read the application section. The user software itself must prevent addressing this section during the Self-Programming operations. This implies that interrupts must be disabled. Before addressing the application section after the programming is completed, for future compatibility, the user software must write "10001" to the five LSB in SPMCR and execute SPM within four clock cycles. Then the user software should verify that the ASB bit is cleared. See "Assembly code example for a Boot Loader" on page 141 for an example. Though the ASB and ASRE bits have no special function in this device, it is important for future code compatibility that they are treated as described above. ATMEGA163 has two separate sets of Boot Lock bits which can be set independently. This gives the user a unique flexibility to select different levels of protection. The user can select: * * * * To protect the entire Flash from a software update by the MCU To only protect the Boot Loader Flash section from a software update by the MCU To only protect application Flash section from a software update by the MCU Allowing software update in the entire Flash Boot Loader Lock Bits See Table and Table for further details. The Boot Lock bits can be set in software and in Serial or Parallel Programming mode, but they can only be cleared by a chip erase command. 137 1142E-AVR-02/03 Table 53. Boot Lock Bit0 Protection Modes (Application Section) (1) BLB0 mode 1 2 3 BLB02 1 1 0 BLB01 1 0 0 Protection No restrictions for SPM, LPM accessing the Application section SPM is not allowed to write to the Application section SPM is not allowed to write to the Application section, and LPM executing from the Boot Loader section is not allowed to read from the Application section LPM executing from the Boot Loader section is not allowed to read from the Application section 4 Note: 0 1 1. "1" means unprogrammed, "0" means programmed Table 54. Boot Lock Bit1 Protection Modes (Boot Loader Section)(1) BLB1 mode 1 2 BLB12 1 1 BLB11 1 0 Protection No restrictions for SPM, LPM accessing the Boot Loader section SPM is not allowed to write to the Boot Loader section SPM is not allowed to write to the Boot Loader section, and LPM executing from the Application section is not allowed to read from the Boot Loader section. If code is executed from Boot section, the interrupts are disabled when BLB12 is programmed. LPM executing from the Application section is not allowed to read from the Boot Loader section. If code is executed from Boot section, the interrupts are disabled when BLB12 is programmed. 3 0 0 4 0 1 Note: 1. "1" means unprogrammed, "0" means programmed Setting the Boot Loader Lock Bits by SPM To set the Boot Loader Lock bits, write the desired data to R0, write "00001001" to SPMCR and execute SPM within four clock cycles after writing SPMCR. The only accessible Lock bits are the Boot Lock bits that may prevent the Application and Boot Loader section from any software update by the MCU. Bit R0 7 1 6 1 5 BLB12 4 BLB11 3 BLB02 2 BLB01 1 1 0 1 If bits 5..2 in R0 are cleared (zero), the corresponding Boot Lock bit will be programmed if an SPM instruction is executed within four cycles after BLBSET and SPMEN are set in SPMCR. Reading the Fuse and Lock Bits from Software It is possible to read both the Fuse and Lock bits from software. To read the Lock bits, load the Z-pointer with $0001 and set the BLBSET and SPMEN bits in SPMCR. When an LPM instruction is executed within five CPU cycles after the BLBSET and SPMEN bits are set in SPMCR, the value of the Lock bits will be loaded in the destination register. The BLBSET and SPMEN bits will auto-clear upon completion of reading the Lock bits or if no SPM, or LPM, instruction is executed within four, respectively five, CPU cycles. When BLBSET and SPMEN are cleared, LPM will work as described in "Constant Addressing Using The LPM and SPM Instructions" on page 15 and in the Instruction set Manual. 138 ATMEGA163(L) 1142E-AVR-02/03 ATMEGA163(L) Bit Rd 7 - 6 - 5 BLB12 4 BLB11 3 BLB02 2 BLB01 1 LB2 0 LB1 The algorithm for reading the Fuse Low bits is similar to the one described above for reading the Lock bits. To read the Fuse Low bits, load the Z-pointer with $0000 and set the BLBSET and SPMEN bits in SPMCR. When an LPM instruction is executed within five cycles after the BLBSET and SPMEN bits are set in the SPMCR, the value of the Fuse Low bits will be loaded in the destination register as shown below. Bit Rd 7 BODLEVEL 6 BODEN 5 SPIEN 4 - 3 CKSEL3 2 CKSEL2 1 CKSEL1 0 CKSEL0 Similarly, when reading the Fuse High bits, load $0003 in the Z-pointer. When an LPM instruction is executed within five cycles after the BLBSET and SPMEN bits are set in the SPMCR, the value of the Fuse High bits will be loaded in the destination register as shown below. Bit Rd 7 - 6 - 5 - 4 - 3 - 2 BOOTSZ1 1 BOOTSZ0 0 BOOTRST Fuse and Lock bits that are programmed, will be read as zero. Fuse and Lock bits that are unprogrammed, will be read as one. In all cases, the read value of unused bit positions are undefined. EEPROM Write Prevents Writing to SPMCR Note that an EEPROM write operation will block all software programming to Flash. Reading the Fuses and Lock bits from software will also be prevented during the EEPROM write operation. It is recommended that the user checks the status bit (EEWE) in the EECR Register and verifies that the bit is cleared before writing to the SPMCR Register. If EEPROM writing is performed inside an interrupt routine, the user software should disable that interrupt before checking the EEWE status bit. The Z-pointer is used to address the SPM commands. Bit ZH (R31) ZL (R30) 15 Z15 Z7 7 14 Z14 Z6 6 13 Z13 Z5 5 12 Z12 Z4 4 11 Z11 Z3 3 10 Z10 Z2 2 9 Z9 Z1 1 8 Z8 Z0 0 Addressing the Flash During Self-Programming Z15:Z14 always ignored Z13:Z7 Z6:Z1 Z0 page select, for page erase and page write word select, for filling temp buffer (must be zero during page write operation) should be zero for all SPM commands, byte select for the LPM instruction. The only operation that does not use the Z-pointer is Setting the Boot Loader Lock bits. The content of the Z-pointer is ignored and will have no effect on the operation. Note that the Page Erase and Page Write operation is addressed independently. Therefore it is of major importance that the Boot Loader software addresses the same page in both the page erase and page write operation. The LPM instruction also uses the Z-pointer to store the address. Since this instruction addresses the Flash byte-by-byte, also the LSB (bit Z0) of the Z-pointer is used. See page 15 for a detailed description. 139 1142E-AVR-02/03 Store Program Memory Control Register - SPMCR The Store Program Memory Control Register contains the control bits needed to control the programming of the Flash from internal code execution. Bit $37 ($57) Read/Write Initial Value 7 - R x 6 ASB R 0 5 - R 0 4 ASRE R/W 0 3 BLBSET R/W 0 2 PGWRT R/W 0 1 PGERS R/W 0 0 SPMEN R/W 0 SPMCR * Bit 7 - Res: Reserved Bit This bit is a reserved bit in the ATMEGA163 and always reads as zero. This bit should be written to zero when writing SPMCR. * Bit 6 - ASB: Application Section Busy Before entering the Application section after a Boot Loader operation (Page Erase or Page Write) the user software must verify that this bit is cleared. In future devices, this bit will be set to "1" by Page Erase and Page Write. In ATMEGA163, this bit always reads as zero. * Bit 5 - Res: Reserved Bit This bit is a reserved bit in the ATMEGA163 and always reads as zero. This bit should be written to zero when writing SPMCR. * Bit 4 - ASRE: Application Section Read Enable Before re-entering the Application section, the user software must set this bit together with the SPMEN bit and execute SPM within four clock cycles. * Bit 3 - BLBSET: Boot Lock Bit Set If this bit is set at the same time as SPMEN, the next SPM instruction within four clock cycles will set Boot Lock bits. Alternatively, an LPM instruction within five cycles will read either the Lock bBits or the Fuse bits. The BLBSET bit will auto-clear upon completion of the SPM or LPM instruction, or if no SPM, or LPM, instruction is executed within four, respectively five, clock cycles. * Bit 2 - PGWRT: Page Write If this bit is set at the same time as SPMEN, the next SPM instruction within four clock cycles executes Page Write, with the data stored in the temporary buffer. The page address is taken from the high part of the Z-pointer. The data in R1 and R0 are ignored. The PGWRT bit will auto-clear upon completion of a page write, or if no SPM instruction is executed within four clock cycles. The CPU is halted during the entire Page Write operation. * Bit 1 - PGERS: Page Erase If this bit is set at the same time as SPMEN, the next SPM instruction within four clock cycles executes Page Erase. The page address is taken from the high part of the Zpointer. The data in R1 and R0 are ignored. The PGERS bit will auto-clear upon completion of a Page Erase, or if no SPM instruction is executed within four clock cycles. The CPU is halted during the entire Page Erase operation. 140 ATMEGA163(L) 1142E-AVR-02/03 ATMEGA163(L) * Bit 0 - SPMEN: Store Program Memory Enable This bit enables the SPM instruction for the next four clock cycles. If set together with either ASRE, BLBSET, PGWRT, or PGERS, the following SPM instruction will have a special meaning, see description above. If only SPMEN is set, the following SPM instruction will store the value in R1:R0 in the temporary page buffer addressed by the Z-pointer. The LSB of the Z-pointer is ignored. The SPMEN bit will auto-clear upon completion of an SPM instruction, or if no SPM instruction is executed within four clock cycles. During Page Erase and Page Write, the SPMEN bit remains high until the operation is completed. Writing any other combination than "10001", "01001", "00101", or "00001" in the lower five bits will have no effect. Preventing Flash Corruption During periods of low VCC, the Flash can be corrupted because the supply voltage is too low for the CPU and the Flash to operate properly. These issues are the same as for board level systems using the Flash, and the same design solutions should be applied. A Flash corruption can be caused by two situations when the voltage is too low. First, a regular write sequence to the Flash requires a minimum voltage to operate correctly. Secondly, the CPU itself can execute instructions incorrectly, if the supply voltage for executing instructions is too low. Flash corruption can easily be avoided by following these design recommendations (one is sufficient): 1. Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can be done be enabling the internal Brown-out Detector (BOD) if the operating voltage matches the detection level. If not, an external low VCC Reset Protection circuit can be used. If a Reset occurs while a write operation is in progress, the write operation will be completed provided that the power supply voltage is sufficient. The total Reset Time must be longer thatn the Flash write time. This can be achieved by holding the External Reset, or by selecting a long Reset Time-out. 2. Keep the AVR core in Power-down sleep mode during periods of low VCC. This will prevent the CPU from attempting to decode and execute instructions, effectively protecting the Flash from unintentional writes. Assembly code example for a Boot Loader ;- the routine writes one page of data from RAM to Flash ; the first data location in RAM is pointed to by the Y pointer (lowest address) ; the first data location in Flash is pointed to by the Z-pointer (lowest address) ;- error handling is not included ;- the routine must be placed inside the boot space ; Only code inside boot loader ; section should be read during Self-Programming. ;- registers used: r0, r1, temp1, temp2, looplo, loophi, spmcrval ; storing and restoring of registers is not included in the routine ; register usage can be optimized at the expense of code size ;- It is assumed that the interrupts are disabled .equ PAGESIZEB = PAGESIZE*2 ;PAGESIZEB is page size in BYTES, not words .org SMALLBOOTSTART Write_page: ; page erase ldi spmcrval, (1< 1142E-AVR-02/03 ; re-enable the Application Section ldi spmcrval, (1< ; execute page write subi ZL, low(PAGESIZEB) ;restore pointer sbci ZH, high(PAGESIZEB) ;not required for PAGESIZEB<=256 ldi spmcrval, (1< ATMEGA163(L) 1142E-AVR-02/03 ATMEGA163(L) sbrc rjmp ret temp1, SPMEN Wait_spm Program and Data Memory Lock Bits The ATMEGA163 provides six Lock bits which can be left unprogrammed ("1") or can be programmed ("0") to obtain the additional features listed in Table 55. The Lock bits can only be erased to "1" with the Chip Erase command. Table 55. Lock Bit Protection Modes Memory Lock Bits LB mode 1 LB1 1 LB2 1 Protection Type No memory lock features enabled for Parallel and Serial Programming. Further programming of the Flash and EEPROM is disabled in Parallel and Serial Programming mode. The Fuse bits are locked in both Serial and Parallel Programming mode.(1) Further programming and verification of the Flash and EEPROM is disabled in Parallel and Serial Programming mode. The Fuse bits are locked in both Serial and Parallel Programming mode.(1) 2 0 1 3 0 0 BLB0 mode 1 2 3 BLB01 1 0 0 BLB02 1 1 0 No restrictions for SPM, LPM accessing the Application section. SPM is not allowed to write to the Application section. SPM is not allowed to write to the Application section, and LPM executing from the Boot Loader section is not allowed to read from the Application section. LPM executing from the Boot Loader section is not allowed to read from the Application section. 4 BLB1 mode 1 2 1 BLB11 1 0 0 BLB12 1 1 No restrictions for SPM, LPM accessing the Boot Loader section. SPM is not allowed to write to the Boot Loader section. SPM is not allowed to write to the Boot Loader section, and LPM executing from the Application section is not allowed to read from the Boot Loader section. If code executed from the Boot Section, the interrupts are disabled when BLB12 is programmed. LPM executing from the Application section is not allowed to read from the Boot Loader section. If code executed from the Boot Section, the interrupts are disabled when BLB12 is programmed. 3 0 0 4 1 0 Note: 1. Program the Fuse bits before programming the Lock bits. 143 1142E-AVR-02/03 Fuse Bits The ATMEGA163 has ten Fuse bits, divided in two groups. The Fuse High bits are BOOTSZ1..0 and BOOTRST, and the Fuse Low bits are BODLEVEL, BODEN, SPIEN, and CKSEL3..0. * * BOOTSZ1..0 select the size and start address of the Boot Flash section according to Table 51 on page 134. Default value is "11" (both unprogrammed). When BOOTRST is programmed ("0"), the Reset Vector is set to the start address of the Boot Flash section, as selected by the BOOTSZ fuses according to Table 51 on page 134. If the BOOTRST is unprogrammed ("1"), the Reset Vector is set to address $0000. Default value is unprogrammed ("1"). The BODLEVEL Fuse selects the Brown-out Detection Level and changes the Startup times, according to Table 4 on page 24 and Table 5 on page 25, respectively. Default value is unprogrammed ("1"). When the BODEN Fuse is programmed ("0"), the Brown-out Detector is enabled. See "Reset and Interrupt Handling" on page 21. Default value is unprogrammed ("1"). When the SPIEN Fuse is programmed ("0"), Serial Program and Data Downloading are enabled. Default value is programmed ("0"). The SPIEN Fuse is not accessible in serial programming mode. CKSEL3..0 select the clock source and the start-up delay after reset, according to Table 1 on page 5 and Table 5 on page 25. Default value is "0010" (Internal RC Oscillator). * * * * The status of the Fuse bits is not affected by Chip Erase. Note that the Fuse bits are locked if Lock bit1 (LB1) is programmed. Program the Fuse bits before programming the Lock bits. Signature Bytes All Atmel microcontrollers have a three-byte signature code which identifies the device. This code can be read in both serial and parallel mode. The three bytes reside in a separate address space. The ATMEGA163 the signature bytes are: 1. $000: $1E (indicates manufactured by Atmel). 2. $001: $94 (indicates 16KB Flash memory). 3. $002: $02 (indicates ATMEGA163 device when $001 is $94). Calibration Byte The ATMEGA163 has a one byte calibration value for the internal RC Oscillator. This byte resides in the high byte of address $000 in the signature address space. During Memory Programming, the external programmer must read this location and program it into a selected location in the normal Flash Program memory. At start-up, the user software must read this Flash location and write the value to the OSCCAL Register. 144 ATMEGA163(L) 1142E-AVR-02/03 ATMEGA163(L) Parallel Programming This section describes how to Parallel Program and verify Flash Program memory, EEPROM Data memory + Program And Data Memory Lock bits and Fuse bits in the ATMEGA163. Pulses are assumed to be at least 500ns unless otherwise noted. In this section, some pins of the ATMEGA163 are referenced by signal names describing their functionality during parallel programming, see Figure 81 and Table 56. Pins not described in the following table are referenced by pin names. The XA1/XA0 pins determine the action executed when the XTAL1 pin is given a positive pulse. The bit coding are shown in Table 57. When pulsing WR or OE, the command loaded determines the action executed. The Command is a byte where the different bits are assigned functions as shown in Table 58. The BS2 pin should be low unless otherwise noted. Figure 81. Parallel Programming ATMEGA163 +5V RDY/BSY OE WR BS1 XA0 XA1 PAGEL +12 V BS2 PD1 PD2 PD3 PD4 PB7 - PB0 Signal Names VCC +5V AVCC DATA PD5 PD6 PD7 RESET PA0 XTAL1 GND AGND Table 56. Pin Name Mapping Signal Name in Programming Mode RDY/BSY OE WR BS1 XA0 XA1 Pin Name PD1 PD2 PD3 PD4 PD5 PD6 I/O O I I I I I Function 0: Device is busy programming, 1: Device is ready for new command Output Enable (Active low) Write Pulse (Active low) Byte Select 1 ("0" selects low byte, "1" selects high byte) XTAL Action Bit 0 XTAL Action Bit 1 145 1142E-AVR-02/03 Table 56. Pin Name Mapping (Continued) Signal Name in Programming Mode PAGEL BS2 DATA Pin Name PD7 PA0 PB7 - 0 I/O I I I/O Function Program Memory Page Load Byte Select 2 ("0" selects low byte, "1" selects 2'nd high byte) Bidirectional Databus (Output when OE is low) Table 57. XA1 and XA0 Coding XA1 0 0 1 1 XA0 0 1 0 1 Action when XTAL1 is Pulsed Load Flash or EEPROM Address (High or low address byte determined by BS1) Load Data (High or Low data byte for Flash determined by BS1) Load Command No Action, Idle Table 58. Command Byte Bit Coding Command Byte 1000 0000 0100 0000 0010 0000 0001 0000 0001 0001 0000 1000 0000 0100 0000 0010 0000 0011 Command Executed Chip Erase Write Fuse Bits Write Lock Bits Write Flash Write EEPROM Read Signature Bytes Read Fuse and Lock Bits Read Flash Read EEPROM Enter Programming Mode The following algorithm puts the device in Parallel Programming mode: 1. Apply 4.5 - 5.5V between VCC and GND. 2. Set RESET and BS pins to "0" and wait at least 100 ns. 3. Apply 11.5 - 12.5V to RESET. Any activity on BS1 within 100 ns after +12V has been applied to RESET, will cause the device to fail entering Programming mode. Chip Erase The Chip Erase command will erase the Flash and EEPROM memories and the Lock bits. The Lock bits are not reset until the Program memory has been completely erased. The Fuse bits are not changed. A Chip Erase must be performed before the Flash is reprogrammed. Load Command "Chip Erase" 1. Set XA1, XA0 to "10". This enables command loading. 2. Set BS1 to "0". 146 ATMEGA163(L) 1142E-AVR-02/03 ATMEGA163(L) 3. Set DATA to "1000 0000". This is the command for Chip Erase. 4. Give WR a negative pulse. This starts the Chip Erase. RDY/BSY goes low. 5. Wait until RDY/BSY goes high before loading a new command. Programming the Flash The Flash is organized as 128 pages of 128 bytes each. When programming the Flash, the program data is latched into a page buffer. This allows one page of program data to be programmed simultaneously. The following procedure describes how to program the entire Flash memory: A. Load Command "Write Flash" 1. Set XA1, XA0 to "10". This enables command loading. 2. Set BS1 to "0". 3. Set DATA to "0001 0000". This is the command for Write Flash. 4. Give XTAL1 a positive pulse. This loads the command. B. Load Address Low Byte 1. Set XA1, XA0 to "00". This enables address loading. 2. Set BS1 to "0". This selects low address. 3. Set DATA = Address Low Byte ($00 - $FF). 4. Give XTAL1 a positive pulse. This loads the address Low Byte. C. Load Data Low Byte 1. Set XA1, XA0 to "01". This enables data loading. 2. Set DATA = Data Low Byte ($00 - $FF). 3. Give XTAL1 a positive pulse. This loads the data byte. D. Latch Data Low Byte 1. Set BS1 to "0". This selects Low Data Byte. 2. Give PAGEL a positive pulse. This latches the data Low Byte. (See Figure 82 for signal waveforms) E. Load Data High Byte 1. Set BS1 to "1". This selects High Data Byte. 2. Set XA1, XA0 to "01". This enables data loading. 3. Set DATA = Data High Byte ($00 - $FF). 4. Give XTAL1 a positive pulse. This loads the data byte. F. Latch Data High Byte 1. Set BS1 to "1". This selects High Data Byte. 2. Give PAGEL a positive pulse. This latches the data High Byte. G. Repeat B through F 64 times to fill the page buffer. To address a page in the Flash, seven bits are needed (128 pages). The five most significant bits are read from address high byte as described in section "H" below. The two least significant page address bits however, are the two most significant bits (bit7 and bit6) of the latest loaded address low byte as described in section "B". 147 1142E-AVR-02/03 H. Load Address High byte 1. 1. Set XA1, XA0 to "00". This enables address loading. 2. Set BS1 to "1". This selects high address. 3. Set DATA = Address High Byte ($00 - $1F). 4. Give XTAL1 a positive pulse. This loads the address High Byte. I. Program Page 1. Give WR a negative pulse. This starts programming of the entire page of data. RDY/BSYgoes low. 2. Wait until RDY/BSY goes high. (See Figure 83 for signal waveforms) J. End Page Programming 1. Set XA1, XA0 to "10". This enables command loading. 2. Set DATA to "0000 0000". This is the command for No Operation. 3. Give XTAL1 a positive pulse. This loads the command, and the internal write signals are reset. K. Repeat A through J 128 times or until all data has been programmed. Figure 82. Programming the Flash Waveforms DATA $10 ADDR. LOW ADDR. HIGH DATA LOW XA1 XA2 BS1 XTAL1 WR DY/BSY RESET +12V OE BS2 PAGEL 148 ATMEGA163(L) 1142E-AVR-02/03 ATMEGA163(L) Figure 83. Programming the Flash Waveforms (continued) DATA DATA HIGH XA1 XA0 BS1 XTAL1 WR RDY/BSY RESET OE PAGEL BS2 +12V Programming the EEPROM The programming algorithm for the EEPROM Data Memory is as follows (refer to "Programming the Flash" on page 147 for details on Command, Address and Data loading): 1. A: Load Command "0001 0001". 2. H: Load Address High Byte ($00 - $01) 3. B: Load Address Low Byte ($00 - $FF) 4. E: Load Data Low Byte ($00 - $FF) L: Write Data Low Byte 1. Set BS to "0". This selects low data. 2. Give WR a negative pulse. This starts programming of the data byte. RDY/BSY goes low. 3. Wait until to RDY/BSY goes high before programming the next byte. (See Figure 84 for signal waveforms) The loaded command and address are retained in the device during programming. For efficient programming, the following should be considered. * * * The command needs only be loaded once when writing or reading multiple memory locations. Address high byte needs only be loaded before programming a new 256 word page in the EEPROM. Skip writing the data value $FF, that is the contents of the entire EEPROM after a Chip Erase. These considerations also applies to Flash, EEPROM and Signature bytes reading. 149 1142E-AVR-02/03 Figure 84. Programming the EEPROM Waveforms DATA $11 ADDR. HIGH ADDR. LOW DATA LOW XA1 XA2 BS1 XTAL1 WR RDY/BSY RESET +12V OE BS2 PAGEL Reading the Flash The algorithm for reading the Flash memory is as follows (refer to "Programming the Flash" on page 147 for details on Command and Address loading): 1. A: Load Command "0000 0010". 2. H: Load Address High Byte ($00 - $1F). 3. B: Load Address Low Byte ($00 - $FF). 4. Set OE to "0", and BS1 to "0". The Flash word low byte can now be read at DATA. 5. Set BS to "1". The Flash word high byte can now be read at DATA. 6. Set OE to "1". Reading the EEPROM The algorithm for reading the EEPROM memory is as follows (refer to "Programming the Flash" on page 147 for details on Command and Address loading): 1. A: Load Command "0000 0011". 2. H: Load Address High Byte ($00 - $01). 3. B: Load Address ($00 - $FF). 4. Set OE to "0", and BS1 to "0". The EEPROM Data byte can now be read at DATA. 5. Set OE to "1". Programming the Fuse Low Bits The algorithm for programming the Fuse Low bits is as follows (refer to "Programming the Flash" on page 147 for details on Command and Data loading): 1. A: Load Command "0100 0000". 2. C: Load Data Low Byte. Bit n = "0" programs and bit n = "1" erases the Fuse bit. Bit 7 = BODLEVEL Fuse bit Bit 6 = BODEN Fuse bit Bit 5 = SPIEN Fuse bit Bit 3..0 = CKSEL3..0 Fuse bits Bit 4 = "1". This bit is reserved and should be left unprogrammed ("1"). 3. Give WR a negative pulse and wait for RDY/BSY to go high. 150 ATMEGA163(L) 1142E-AVR-02/03 ATMEGA163(L) Programming the Fuse High Bits The algorithm for programming the Fuse high bits is as follows (refer to "Programming the Flash" on page 147 for details on Command and Data loading): 1. A: Load Command "0100 0000". 2. C: Load Data Low Byte. Bit n = "0" programs and bit n = "1" erases the Fuse bit. Bit 2..1 = BOOTSZ1..0 Fuse bits Bit 0 = BOOTRST Fuse bit Bit 7..3 = "1". These bits are reserved and should be left unprogrammed ("1"). 3. Set BS1 to "1". This selects high data byte. 4. Give WR a negative pulse and wait for RDY/BSY to go high. 5. Set BS1 to "0". This selects low data byte. Programming the Lock Bits The algorithm for programming the Lock bits is as follows (refer to "Programming the Flash" on page 147 for details on Command and Data loading): 1. A: Load Command "0010 0000". 2. D: Load Data Low Byte. Bit n = "0" programs the Lock bit. Bit 5 = Boot Lock bit12 Bit 4 = Boot Lock bit11 Bit 3 = Boot Lock bit02 Bit 2 = Boot Lock bit01 Bit 1 = Lock bit2 Bit 0 = Lock bit1 Bit 7..6 = "1". These bits are reserved and should be left unprogrammed ("1"). 3. L: Write Data Low Byte. The Lock bits can only be cleared by executing Chip Erase. Reading the Fuse and Lock Bits The algorithm for reading the Fuse and Lock bits is as follows (refer to "Programming the Flash" on page 147 for details on Command loading): 1. A: Load Command "0000 0100". 2. Set OE to "0", BS2 to "0" and BS1 to "0". The status of the Fuse Low bits can now be read at DATA ("0" means programmed). Bit 7 = BODLEVEL Fuse bit Bit 6 = BODEN Fuse bit Bit 5 = SPIEN Fuse bit Bit 3..0 = CKSEL3..0 Fuse bits 3. Set OE to "0", BS2 to "1" and BS1 to "1". The status of the Fuse High bits can now be read at DATA ("0" means programmed). Bit 2..1 = BOOTSZ1..0 Fuse bits Bit 0 = BOOTRST Fuse bit 4. Set OE to "0", BS2 to "0" and BS1 to "1". The status of the Lock bits can now be read at DATA ("0" means programmed). Bit 5 = Boot Lock bit12 Bit 4 = Boot Lock bit11 Bit 3 = Boot Lock bit02 Bit 2 = Boot Lock bit01 Bit 1 = Lock bit2 Bit 0 = Lock bit1 5. Set OE to "1". 151 1142E-AVR-02/03 Reading the Signature Bytes The algorithm for reading the Signature bytes is as follows (refer to Programming the Flash for details on Command and Address loading): 1. A: Load Command "0000 1000". 2. C: Load Address Low Byte ($00 - $02). 3. Set OE to "0", and BS to "0". The selected Signature byte can now be read at DATA. 4. Set OE to "1". Reading the Calibration Byte The algorithm for reading the Calibration byte is as follows (refer to Programming the Flash for details on Command and Address loading): 1. A: Load Command "0000 1000". 2. C: Load Address Low Byte, $00. Set OE to "0", and BS1 to "1". The Calibaration byte can now be read at DATA. 3. Set OE to "1". 152 ATMEGA163(L) 1142E-AVR-02/03 ATMEGA163(L) Parallel Programming Characteristics Figure 85. Parallel Programming Timing tXLWL XTAL1 tDVXH Data & Contol (DATA, XA0/1, BS1, BS2) tBVPH PAGEL WR RDY/BSY tWLRH tOLDV tPHPL tPLWL WLRL tXHXL tXLDX tPLBX t BVWL tWLWH tRHBX DATA Table 59. Parallel Programming Characteristics, TA = 25C 10%, VCC = 5 V 10% Symbol VPP IPP tDVXH tXHXL tXLDX tXLWL tBVPH tPHPL tPLBX tPLWL tBVWL tRHBX tWLWH tWLRL tWLRH tWLRH_CE tWLRH_FLASH tXLOL tOLDV tOHDZ Notes: 1. Parameter Programming Enable Voltage Programming Enable Current Data and Control Valid before XTAL1 High XTAL1 Pulse Width High Data and Control Hold after XTAL1 Low XTAL1 Low to WR Low BS1 Valid before PAGEL High PAGEL Pulse Width High BS1 Hold after PAGEL Low PAGEL Low to WR Low BS1 Valid to WR Low BS1 Hold after RDY/BSY High WR Pulse Width Low WR Low to RDY/BSY Low WR Low to RDY/BSY High (1) (2) Min 11.5 Typ Max 12.5 250 Units V A ns ns ns ns ns ns ns ns ns ns ns 67 67 67 67 67 67 67 67 67 67 67 0 1 16 8 67 20 20 1.5 23 12 2.5 1.9 30 15 s ms ms ms ns ns ns WR Low to RDY/BSY High for Chip Erase WR Low to RDY/BSY High for Write Flash(3) XTAL1 Low to OE Low OE Low to DATA Valid OE High to DATA Tri-stated tWLRH is valid for the Write EEPROM, Write Fuse Bits and Write Lock Bits commands. 2. tWLRH_CE is valid for the Chip Erase command. 3. tWLRH_FLASH is valid for the Write Flash command. 153 1142E-AVR-02/03 Read OE tXLOL tOHDZ Write Serial Downloading Both the Flash and EEPROM memory arrays can be programmed using the serial SPI bus while RESET is pulled to GND. The serial interface consists of pins SCK, MOSI (input) and MISO (output). After RESET is set low, the Programming Enable instruction needs to be executed first before program/erase operations can be executed. Figure 86. Serial Programming and Verify(1) ATMEGA163 2.7 - 5.5V VCC 2.7 - 5.5V MOSI MISO SCK PB5 PB6 PB7 XTAL1 AVCC (2) RESET GND AGND Notes: 1. If the device is clocked by the internal Oscillator, connecting a clock source to XTAL1 is not required. 2. VCC - 0.3 V < AVCC < VCC + 0.3 V, however, AVCC should always be within 2.7 5.5 V. When programming the EEPROM, an auto-erase cycle is built into the self-timed programming operation (in the Serial mode ONLY) and there is no need to first execute the Chip Erase instruction. The Chip Erase operation turns the content of every memory location in both the Program and EEPROM arrays into $FF. The Program and EEPROM memory arrays have separate address spaces: $0000 to $1FFF for Program memory and $0000 to $01FF for EEPROM memory. The device can be clocked by any clock option during Serial Programming. The minimum low and high periods for the serial clock (SCK) input are defined as follows: Low: > 2 MCU clock cycles High: > 2 MCU clock cycles 154 ATMEGA163(L) 1142E-AVR-02/03 ATMEGA163(L) Serial Programming Algorithm When writing serial data to the ATMEGA163, data is clocked on the rising edge of SCK. When reading data from the ATMEGA163, data is clocked on the falling edge of SCK. See Figure 87, Figure 88 and Table 62 for timing details. To program and verify the ATMEGA163 in the serial programming mode, the following sequence is recommended (See four byte instruction formats in Table 61): 1. Power-up sequence: Apply power between VCC and GND while RESET and SCK are set to "0". In accordance with the setting of CKSEL Fuses, apply a crystal/resonator, external clock, or RC network, or let the device run on the internal RC Oscillator. In some systems, the programmer can not guarantee that SCK is held low during power-up. In this case, wait for 100 ms after SCK has been set to "0". RESET must be then given a positive pulse of at least two XTAL1 cycles duration and then set to "0". 2. Wait for at least 20 ms and enable serial programming by sending the Programming Enable serial instruction to pin MOSI/PB5. 3. The Serial Programming instructions will not work if the communication is out of synchronization. When in sync. the second byte ($53), will echo back when issuing the third byte of the Programming Enable instruction. Whether the echo is correct or not, all four bytes of the instruction must be transmitted. If the $53 did not echo back, give SCK a positive pulse and issue a new Programming Enable command. If the $53 is not seen within 32 attempts, there is no functional device connected. 4. If a Chip Erase is performed (must be done to erase the Flash), wait 2*tWD_FLASH after the instruction, give RESET a positive pulse, and start over from Step 2. See Table 60 for the tWD_FLASH figure. 5. The Flash is programmed one page at a time. The memory page is loaded one byte at a time by supplying the 6 LSB of the address and data together with the Load Program Memory Page instruction. The Program Memory Page is stored by loading the Write Program Memory Page instruction with the 7 MSB of the address. If polling is not used, the user must wait at least tWD_FLASH before issuing the next page. (Please refer to Table 60). Accessing the serial programming interface before the Flash write operation completes can result in incorrect programming. 6. The EEPROM array is programmed one byte at a time by supplying the address and data together with the appropriate Write instruction. An EEPROM memory location is first automatically erased before new data is written. If polling is not used, the user must wait at least tWD_EEPROM before issuing the next byte. (Please refer to Table 60). In a chip erased device, no $FFs in the data file(s) need to be programmed. 7. Any memory location can be verified by using the Read instruction which returns the content at the selected address at serial output MISO/PB6. 8. At the end of the programming session, RESET can be set high to commence normal operation. 9. Power-off sequence (if needed): Set XTAL1 to "0" (if external clock is used). Set RESET to "1". Turn VCC power-off. 155 1142E-AVR-02/03 Data Polling Flash When a page is being programmed into the Flash, reading an address location within the page being programmed will give the value $FF. At the time the device is ready for a new page, the programmed value will read correctly. This is used to determine when the next page can be written. Note that the entire page is written simultaneously and any address within the page can be used for polling. Data polling of the Flash will not work for the value $FF, so when programming this value, the user will have to wait for at least tWD_FLASH before programming the next page. As a chip-erased device contains $FF in all locations, programming of addresses that are meant to contain $FF, can be skipped. See Table 60 for tWD_FLASH value. When a new byte has been written and is being programmed into EEPROM, reading the address location being programmed will give the value $FF. At the time the device is ready for a new byte, the programmed value will read correctly. This is used to determine when the next byte can be written. This will not work for the value $FF, but the user should have the following in mind: As a chip-erased device contains $FF in all locations, programming of addresses that are meant to contain $FF, can be skipped. This does not apply if the EEPROM is re-programmed without chip-erasing the device. In this case, data polling cannot be used for the value $FF, and the user will have to wait at least tWD_EEPROM before programming the next byte. See Table 60 for tWD_EEPROM value. The internal RC Oscillator is used to control programming time when programming or erasing Flash, EEPORM, Fuses, and Lock bits. During Parallel or Serial Programming, the device is in reset, and this Oscillator runs at its initial, uncalibrated frequency, which may vary from 0.5 MHz to 1.0 MHz. In software it is possible to calibrate this Oscillator to 1.0 MHz (see "Calibrated Internal RC Oscillator" on page 37). Consequently, programming times will be shorter and more accurate when Programming or erasing non-volatile memory from software, using SPM or the EEPROM interface. See Table 60 for a summary of programming times. Table 60. Maximum Programming Times for Non-volatile Memory Number of RC Oscillator Cycles 16K 8K 2K 1K Parallel/Serial Programming 2.7V 32 ms 16 ms 4 ms 2 ms 5.0V 30 ms 15 ms 3.8 ms 1.9 ms SelfProgramming(1) 17 ms 8.5 ms 2.2 ms 1.1 ms Data Polling EEPROM Programming Times for Nonvolatile Memory Operation Chip Erase Flash Write(3) EEPROM Write(2) Fuse/lock bit write Notes: Symbol tWD_CE tWD_FLASH tWD_EEPROM tWD_FUSE 1. Includes variation over voltage and temperature after RC Oscillator has been calibrated to 1.0 MHz 2. Parallel EEPROM Programming takes 1K cycles 3. Per page 156 ATMEGA163(L) 1142E-AVR-02/03 ATMEGA163(L) Figure 87. Serial Programming Waveforms SERIAL DATA INPUT PB5 (MOSI) SERIAL DATA OUTPUT PB6 (MISO) SERIAL CLOCK INPUT PB7(SCK) SAMPLE MSB LSB MSB LSB 157 1142E-AVR-02/03 . Table 61. Serial Programming Instruction Set Instruction Format Instruction Programming Enable Chip Erase Read Program Memory Load Program Memory Page Write Program Memory Page Read EEPROM Memory Write EEPROM Memory Read Lock Bits Write Lock Bits Read Signature Byte Write Fuse Bits Write Fuse High Bits Read Fuse Bits Read Fuse High Bits Read Calibration Byte Note: Byte 1 1010 1100 1010 1100 0010 H000 0100 H000 0100 1100 1010 0000 1100 0000 0101 1000 1010 1100 0011 0000 1010 1100 1010 1100 0101 0000 Byte 2 0101 0011 100x xxxx xxxa aaaa xxxx xxxx xxxa aaaa xxxx xxxa xxxx xxxa 0000 0000 111x xxxx xxxx xxxx 1010 0000 1010 1000 0000 0000 Byte 3 xxxx xxxx xxxx xxxx bbbb bbbb xxbb bbbb bbxx xxxx bbbb bbbb bbbb bbbb xxxx 0xxx xxxx xxxx xxxx xxbb xxxx xxxx xxxx xxxx xxxx xxxx Byte4 xxxx xxxx xxxx xxxx oooo oooo iiii iiii xxxx xxxx oooo oooo iiii iiii xx65 4321 1165 4321 oooo oooo CB11 A987 1111 1FED CBxx A987 Operation Enable Serial Programming after RESET goes low. Chip Erase EEPROM and Flash. Read H (high or low) data o from Program memory at word address a:b. Write H (high or low) data i to Program Memory page at word address b. Write Program Memory Page at address a:b. Read data o from EEPROM memory at address a:b. Write data i to EEPROM memory at address a:b. Read Lock bits. "0" = programmed, "1" = unprogrammed. Write Lock bits. Set bits 6 - 1 = "0" to program Lock bits. Read Signature Byte o at address b. Set bits C - A, 9 - 7 = "0" to program, "1" to unprogram Set bits F - D = "0" to program, "1" to unprogram Read Fuse bits. "0" = programmed, "1" = unprogrammed Read Fuse high bits. "0" = programmed, "1" = unprogrammed Read Signature Byte o at address b. 0101 1000 0011 1000 0000 1000 xxxx xxxx xxxx xxxx 0000 0000 xxxx 1FED oooo oooo a = address high bits, b = address low bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don't care 1 = lock bit 1, 2 = lock bit 2, 3 = Boot Lock Bit01, 4 = Boot Lock Bit02, 5 = Boot Lock Bit11, 6 = Boot Lock Bit12, 7 = CKSEL0 Fuse, 8 = CKSEL1 Fuse, 9 = CKSEL2 Fuse, A = CKSEL3 Fuse, B= BODEN Fuse, C= BODLEVEL Fuse, D= BOOTRST Fuse, E= BOOTSZ0 Fuse, F= BOOTSZ1 Fuse 158 ATMEGA163(L) 1142E-AVR-02/03 ATMEGA163(L) Serial Programming Characteristics Figure 88. Serial Programming Timing MOSI tOVSH SCK MISO tSLIV tSHSL tSHOX tSLSH Table 62. Serial Programming Characteristics, TA = -40C to 85C, VCC = 2.7V - 5.5V (Unless otherwise noted) Symbol 1/tCLCL tCLCL 1/tCLCL tCLCL tSHSL tSLSH tOVSH tSHOX tSLIV Parameter Oscillator Frequency (VCC = 2.7 - 5.5 V) Oscillator Period (VCC = 2.7 - 5.5 V) Oscillator Frequency (VCC = 4.0 - 5.5 V) Oscillator Period (VCC = 4.0 - 5.5 V) SCK Pulse Width High SCK Pulse Width Low MOSI Setup to SCK High MOSI Hold after SCK High SCK Low to MISO Valid Min 0 250 0 125 2 tCLCL 2 tCLCL tCLCL 2 tCLCL 10 16 32 8 Typ Max 4 Units MHz ns MHz ns ns ns ns ns ns 159 1142E-AVR-02/03 Electrical Characteristics Absolute Maximum Ratings* Operating Temperature ................................. -55C to +125C Storage Temperature .................................... -65C to +150C Voltage on any Pin except RESET with respect to Ground ................................-1.0V to VCC +0.5V Voltage on RESET with respect to Ground .....-1.0V to +13.0V Maximum Operating Voltage ............................................ 6.6V DC Current per I/O Pin ............................................... 40.0 mA DC Current VCC and GND Pins................................ 200.0 mA *NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC Characteristics TA = -40C to 85C, VCC = 2.7V to 5.5V (unless otherwise noted) Symbol VIL Parameter Input Low-voltage Condition (Except XTAL1) (XTAL1), CKSEL3 fuse programmed VIL1 Input Low-voltage (XTAL1), CKSEL3 fuse unprogrammed Input High-voltage (Except XTAL1, RESET) (XTAL1), CKSEL3 fuse programmed VIH1 Input High-voltage (XTAL1), CKSEL3 fuse unprogrammed Input High-voltage Output Low-voltage (Ports A,B,C,D) (3) Min -0.5 -0.5 -0.5 0.6 VCC(2) 0.6 VCC(2) 0.8 VCC(2) 0.9 VCC(2) Typ Max 0.3 VCC (1) Units V V V V V V V V V V V 0.3 VCC(1) 0.2 VCC(1) VCC + 0.5 VCC + 0.5 VCC + 0.5 VCC + 0.5 0.6 0.5 VIH VIH2 VOL VOH IIL IIH RRST RI/O (RESET) IOL = 20 mA, V CC = 5V IOL = 10 mA, V CC = 3V IOH = -3 mA, VCC = 5V IOH = -1.5 mA, VCC = 3V Vcc = 5.5V, pin low (absolute value) Vcc = 5.5V, pin high (absolute value) Output High-voltage(4) (Ports A,B,C,D) Input Leakage Current I/O pin Input Leakage Current I/O pin Reset Pull-up Resistor I/O Pin Pull-up Resistor 4.2 2.3 8.0 980 100 35 500 120 A nA k k 160 ATMEGA163(L) 1142E-AVR-02/03 ATMEGA163(L) DC Characteristics Symbol Parameter (Continued) TA = -40C to 85C, VCC = 2.7V to 5.5V (unless otherwise noted) Condition Active 4 MHz, VCC = 3V (ATMEGA163L) Active 8 MHz, VCC = 5V (ATMEGA163) Power Supply Current ICC Idle 4 MHz, VCC = 3V (ATMEGA163L) Idle 8 MHz, VCC = 5V (ATMEGA163) Power-down mode(5) Analog Comparator Input Offset Voltage Analog Comparator Input Leakage Current Analog Comparator Initialization Delay WDT enabled, VCC = 3V WDT disabled, VCC = 3V VACIO IACLK tACID Notes: VCC = 5V Vin = VCC/2 VCC = 5V Vin = VCC/2 VCC = 2.7V VCC = 4.0V -50 750 500 9 <1 2.5 8 15.0 4.0 40 50 mA mA A A mV nA ns Min Typ Max 5.0 15.0 Units mA mA 1. "Max" means the highest value where the pin is guaranteed to be read as low 2. "Min" means the lowest value where the pin is guaranteed to be read as high 3. Although each I/O port can sink more than the test conditions (20 mA at Vcc = 5V, 10 mA at Vcc = 3V) under steady state conditions (non-transient), the following must be observed: 1] The sum of all IOL, for all ports, should not exceed 200 mA. 2] The sum of all IOL, for ports B0 - B7, D0 - D7 and XTAL2, should not exceed 100 mA. 3] The sum of all IOL, for ports A0 - A7 and C0 - C7 should not exceed 100 mA. If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test condition. 4. Although each I/O port can source more than the test conditions (3 mA at Vcc = 5V, 1.5 mA at Vcc = 3V) under steady state conditions (non-transient), the following must be observed: 1] The sum of all IOH, for all ports, should not exceed 200 mA. 2] The sum of all IOH, for ports B0 - B7, D0 - D7 and XTAL2, should not exceed 100 mA. 3] The sum of all IOH, for ports A0 - A7 and C0 - C7 should not exceed 100 mA. If IOH exceeds the test condition, VOH may exceed the related specification. Pins are not guaranteed to source current greater than the listed test condition. 5. Minimum VCC for Power-down is 2.5V. External Clock Drive Waveforms Figure 89. External Clock Drive Waveforms 161 1142E-AVR-02/03 External Clock Drive Table 63. External Clock Drive VCC = 2.7V to 5.5V Symbol 1/tCLCL tCLCL tCHCX tCLCX tCLCH tCHCL Parameter Oscillator Frequency Clock Period High Time Low Time Rise Time Fall Time Min 0 250 100 100 1.6 1.6 Max 4 VCC = 4.0V to 5.5V Min 0 125 50 50 0.5 0.5 Max 8 Units MHz ns ns ns s s Table 64. External RC Oscillator, typical frequencies R [k] 100 31.5 6.5 Note: C [pF] 70 20 20 f 100 kHz 1.0 MHz 4.0 MHz R should be in the range 3k - 100k, and C should be at least 20pF. The C values given in the table includes pin capacitance. This will vary with package type. 162 ATMEGA163(L) 1142E-AVR-02/03 ATMEGA163(L) Two-wire Serial Interface Characteristics Table 65 describes the requirements for devices connected to the Two-wire Serial Bus. The ATMEGA163 Two-wire Serial Interface meets or exceeds these requirements under the noted conditions. Timing symbols refer to Figure 90. Table 65. Two-wire Serial Bus Requirements Symbol VIL VIH Vhys (1) Parameter Input Low-voltage Input High-voltage Hysteresis of Schmitt Trigger Inputs Output Low-voltage Output Fall Time from VIHmin to VILmax Spikes Suppressed by Input Filter Input Current each I/O Pin Capacitance for each I/O Pin SCL Clock Frequency fCK (4) Condition Min -0.5 0.7 VCC 0.05 VCC (2) Max 0.3 VCC VCC + 0.5 - 0.4 (3)(2) Units V V V V ns ns A pF kHz s s s s s s s s s s ns ns s s s s VOL(1) tof(1) tSP(1) Ii Ci(1) fSCL tHD;STA 3 mA sink current 10 pF < Cb < 400 pF (3) 0 20 + 0.1Cb 0 250 50 (2) 0.1VCC < V i < 0.9VCC -10 - 10 10 217 - - - - - - - - 3.45 0.9 - - - - - - > max(16fSCL, 250kHz) fSCL 100 kHz (5) 0 4.0 0.6 4.7 1.3 4.0 0.6 4.7 0.6 0 0 250 100 4.0 0.6 4.7 1.3 Hold Time (repeated) START Condition fSCL > 100 kHz fSCL 100 kHz(6) tLOW Low Period of the SCL Clock fSCL > 100 kHz fSCL 100 kHz tHIGH High period of the SCL clock fSCL > 100 kHz fSCL 100 kHz tSU;STA Set-up time for a repeated START condition fSCL > 100 kHz fSCL 100 kHz tHD;DAT Data hold time fSCL > 100 kHz fSCL 100 kHz tSU;DAT Data setup time fSCL > 100 kHz fSCL 100 kHz tSU;STO Setup time for STOP condition Bus free time between a STOP and START condition 1. 2. 3. 4. 5. fSCL > 100 kHz fSCL 100 kHz fSCL > 100 kHz tBUF Notes: In ATmegan163, this parameter is characterized and not 100% tested. Required only for fSCL > 100 kHz. Cb = capacitance of one bus line in pF. fCK = CPU clock frequency This requirement applies to all ATMEGA163 Two-wire Serial Interface operation. Other devices connected to the Two-wire Serial Bus need only obey the general fSCL requirement. 6. The actual low period generated by the ATMEGA163 Two-wire Serial Interface is (1/fSCL - 2/fCK), thus fCK must be greater than 6 MHz for the low time requirement to be strictly met at fSCL = 100 kHz. 163 1142E-AVR-02/03 Figure 90. Two-wire Serial Bus Timing tof tLOW SCL tSU;STA SDA tHD;STA tHD;DAT tSU;DAT tSU;STO tHIGH tLOW tBUF 164 ATMEGA163(L) 1142E-AVR-02/03 ATMEGA163(L) Typical Characteristics The following charts show typical behavior. These figures are not tested during manufacturing. All current consumption measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled. All pins on Port F are pulled high externally. A sine wave generator with rail-to-rail output is used as clock source. The power consumption in Power-down mode is independent of clock selection. The current consumption is a function of several factors such as: operating voltage, operating frequency, loading of I/O pins, switching rate of I/O pins, code executed and ambient temperature. The dominating factors are operating voltage and frequency. The current drawn from capacitive loaded pins may be estimated (for one pin) as CL * VCC * f, where CL = load capacitance, VCC = operating voltage and f = average switching frequency of I/O pin. The parts are characterized at frequencies higher than test limits. Parts are not guaranteed to function properly at frequencies higher than the ordering code indicates. The difference between current consumption in Power-down mode with Watchdog Timer enabled and Power-down mode with Watchdog Timer disabled represents the differential current drawn by the Watchdog Timer. Figure 91. Analog Comparator Offset Voltage vs, Common Mode Voltage (VCC = 5V) 18 16 14 Offset Voltage (mV) 12 10 8 6 4 2 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 TA = 25C TA = 85C Common Mode Voltage (V) 165 1142E-AVR-02/03 Figure 92. Analog Comparator Offset Voltage vs. Common Mode Voltage (VCC = 2.7V) 10 TA = 25C 8 Offset Voltage (mV) 6 TA = 85C 4 2 0 0 0.5 1 1.5 Common Mode Voltage (V) 2 2.5 3 Figure 93. Analog Comparator Input Leakage Current (VCC = 6V; TA = 25C) 60 50 40 ACLK (nA) 30 20 10 0 -10 0 0.5 1 1.5 2 2.5 3 3.5 VIN (V) I 4 4.5 5 5.5 6 6.5 7 166 ATMEGA163(L) 1142E-AVR-02/03 ATMEGA163(L) Figure 94. Watchdog Oscillator Frequency vs. VCC 1600 TA = 25C 1400 1200 1000 800 600 400 200 0 2 2.5 3 3.5 4 Vcc (V) TA = 85C F RC (KHz) 4.5 5 5.5 6 Sink and source capabilities of I/O ports are measured on one pin at a time. Figure 95. Pull-up Resistor Current vs. Input Voltage (VCC = 5V) 120 TA = 25C 100 TA = 85C 80 OP (A) I 60 40 20 0 0 0.5 1 1.5 2 2.5 VOP (V) 3 3.5 4 4.5 5 167 1142E-AVR-02/03 Figure 96. Pull-up Resistor Current vs. Input Voltage (VCC = 2.7V) 30 TA = 25C 25 TA = 85C 20 OP (A) 15 I 10 5 0 0 0.5 1 1.5 VOP (V) 2 2.5 3 Figure 97. I/O Pin Sink Current vs. Output Voltage (VCC = 5V) 70 TA = 25C 60 TA = 85C 50 40 OL (mA) 30 20 10 0 0 0.5 1 1.5 VOL (V) 2 2.5 3 168 ATMEGA163(L) 1142E-AVR-02/03 I ATMEGA163(L) Figure 98. I/O Pin Source Current vs. Output Voltage (VCC = 5V) 20 18 16 14 12 OH (mA) TA = 25C TA = 85C 10 8 6 4 2 0 0 0.5 1 1.5 2 2.5 VOH (V) 3 3.5 4 4.5 5 Figure 99. I/O Pin Sink Current vs. Output Voltage (VCC = 2.7V) I 25 TA = 25C 20 TA = 85C 15 OL (mA) 10 I 5 0 0 0.5 1 VOL (V) 1.5 2 169 1142E-AVR-02/03 Figure 100. I/O Pin Source Current vs. Output Voltage (VCC = 2.7V) 6 TA = 25C 5 TA = 85C 4 OH (mA) 3 I 2 1 0 0 0.5 1 1.5 VOH (V) 2 2.5 3 Figure 101. I/O Pin Input Threshold vs. VCC (TA = 25C) 2.5 2 Threshold Voltage (V) 1.5 1 0.5 0 2.7 4.0 Vcc 5.0 170 ATMEGA163(L) 1142E-AVR-02/03 ATMEGA163(L) Figure 102. I/O Pin Input Hysteresis vs. VCC (TA = 25C) 0.18 0.16 0.14 Input hysteresis (V) 0.12 0.1 0.08 0.06 0.04 0.02 0 2.7 4.0 Vcc 5.0 171 1142E-AVR-02/03 Register Summary Address $3F ($5F) $3E ($5E) $3D ($5D) $3C ($5C) $3B ($5B) $3A ($5A) $39 ($59) $38 ($58) $37 ($57) $36 ($56) $35 ($55) $34 ($54) $33 ($53) $32 ($52) $31 ($51) $30 ($50) $2F ($4F) $2E ($4E) $2D ($4D) $2C ($4C) $2B ($4B) $2A ($4A) $29 ($49) $28 ($48) $27 ($47) $26 ($46) $25 ($45) $24 ($44) $23 ($43) $22 ($42) $21 ($41) $20 ($40) $1F ($3F) $1E ($3E) $1D ($3D) $1C ($3C) $1B ($3B) $1A ($3A) $19 ($39) $18 ($38) $17 ($37) $16 ($36) $15 ($35) $14 ($34) $13 ($33) $12 ($32) $11 ($31) $10 ($30) $0F ($2F) $0E ($2E) $0D ($2D) $0C ($2C) $0B ($2B) $0A ($2A) $09 ($29) $08 ($28) $07 ($27) $06 ($26) $05 ($25) $04 ($24) $03 ($23) $02 ($22) $01 ($21) Name SREG SPH SPL Reserved GIMSK GIFR TIMSK TIFR SPMCR TWCR MCUCR MCUSR TCCR0 TCNT0 OSCCAL SFIOR TCCR1A TCCR1B TCNT1H TCNT1L OCR1AH OCR1AL OCR1BH OCR1BL ICR1H ICR1L TCCR2 TCNT2 OCR2 ASSR WDTCR UBRRHI EEARH EEARL EEDR EECR PORTA DDRA PINA PORTB DDRB PINB PORTC DDRC PINC PORTD DDRD PIND SPDR SPSR SPCR UDR UCSRA UCSRB UBRR ACSR ADMUX ADCSR ADCH ADCL TWDR TWAR TWSR Bit 7 I - SP7 Bit 6 T - SP6 Bit 5 H - SP5 Bit 4 S - SP4 Bit 3 V - SP3 - - OCIE1B OCF1B BLBSET TWWC ISC11 WDRF - Bit 2 N SP10 SP2 - - TOIE1 TOV1 PGWRT TWEN ISC10 BORF CS02 Bit 1 Z SP9 SP1 - - - - PGERS - ISC01 EXTRF CS01 Bit 0 C SP8 SP0 - - TOIE0 TOV0 SPMEN TWIE ISC00 PORF CS00 Page 20 21 21 30 31 32 32 140 82 34 28 41 42 37 40 44 45 46 46 47 47 47 47 48 48 52 53 54 57 60 78 62 62 62 63 115 115 115 117 117 117 123 123 123 128 128 128 69 68 67 74 74 76 78 102 110 111 112 112 84 85 84 INT1 INT0 - - INTF1 INTF0 - - OCIE2 TOIE2 TICIE1 OCIE1A OCF2 TOV2 ICF1 OCF1A - ASB - ASRE TWINT TWEA TWSTA TWSTO - SE SM1 SM0 - - - - - - - - Timer/Counter0 (8 Bits) Oscillator Calibration Register - - - - COM1A1 COM1A0 COM1B1 COM1B0 ICNC1 ICES1 - - Timer/Counter1 - Counter Register High Byte Timer/Counter1 - Counter Register Low Byte Timer/Counter1 - Output Compare Register A High Byte Timer/Counter1 - Output Compare Register A Low Byte Timer/Counter1 - Output Compare Register B High Byte Timer/Counter1 - Output Compare Register B Low Byte Timer/Counter1 - Input Capture Register High Byte Timer/Counter1 - Input Capture Register Low Byte FOC2 PWM2 COM21 COM20 Timer/Counter2 (8 Bits) Timer/Counter2 Output Compare Register - - - - - - - WDTOE - - - - - - - - EEAR7 EEAR6 EEAR5 EEAR4 EEPROM Data Register - - - - PORTA7 PORTA6 PORTA5 PORTA4 DDA7 DDA6 DDA5 DDA4 PINA7 PINA6 PINA5 PINA4 PORTB7 PORTB6 PORTB5 PORTB4 DDB7 DDB6 DDB5 DDB4 PINB7 PINB6 PINB5 PINB4 PORTC7 PORTC6 PORTC5 PORTC4 DDC7 DDC6 DDC5 DDC4 PINC7 PINC6 PINC5 PINC4 PORTD7 PORTD6 PORTD5 PORTD4 DDD7 DDD6 DDD5 DDD4 PIND7 PIND6 PIND5 PIND4 SPI Data Register SPIF WCOL - - SPIE SPE DORD MSTR UART I/O Data Register RXC TXC UDRE FE RXCIE TXCIE UDRIE RXEN UART Baud Rate Register ACD ACBG ACO ACI REFS1 REFS0 ADLAR MUX4 ADEN ADSC ADFR ADIF ADC Data Register High Byte ADC Data Register Low Byte Two-wire Serial Interface Data Register TWA6 TWA5 TWA4 TWA3 TWS7 TWS6 TWS5 TWS4 ACME FOC1A CTC1 PUD FOC1B CS12 PSR2 PWM11 CS11 PSR10 PWM10 CS10 CTC2 CS22 CS21 CS20 AS2 WDE - EEAR3 EERIE PORTA3 DDA3 PINA3 PORTB3 DDB3 PINB3 PORTC3 DDC3 PINC3 PORTD3 DDD3 PIND3 - CPOL OR TXEN ACIE MUX3 ADIE TCN2UB OCR2UB WDP2 WDP1 UBRR[11:8] - - EEAR2 EEAR1 EEMWE PORTA2 DDA2 PINA2 PORTB2 DDB2 PINB2 PORTC2 DDC2 PINC2 PORTD2 DDD2 PIND2 - CPHA - CHR9 ACIC MUX2 ADPS2 EEWE PORTA1 DDA1 PINA1 PORTB1 DDB1 PINB1 PORTC1 DDC1 PINC1 PORTD1 DDD1 PIND1 - SPR1 U2X RXB8 ACIS1 MUX1 ADPS1 TCR2UB WDP0 EEAR8 EEAR0 EERE PORTA0 DDA0 PINA0 PORTB0 DDB0 PINB0 PORTC0 DDC0 PINC0 PORTD0 DDD0 PIND0 SPI2X SPR0 MPCM TXB8 ACIS0 MUX0 ADPS0 TWA2 TWS3 TWA1 - TWA0 - TWGCE - 172 ATMEGA163(L) 1142E-AVR-02/03 ATMEGA163(L) Register Summary (Continued) Address $00 ($20) Name TWBR Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page 82 Two-wire Serial Interface Bit Rate Register Note: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 2. Some of the Status Flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate on all bits in the I/O Register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions work with registers $00 to $1F only. 173 1142E-AVR-02/03 Instruction Set Summary Mnemonics Operands Description Operation Rd Rd + Rr Rd Rd + Rr + C Rdh:Rdl Rdh:Rdl + K Rd Rd - Rr Rd Rd - K Rd Rd - Rr - C Rd Rd - K - C Rdh:Rdl Rdh:Rdl - K Rd Rd * Rr Rd Rd * K Rd Rd v Rr Rd Rd v K Rd Rd Rr Rd $FF - Rd Rd $00 - Rd Rd Rd v K Rd Rd * ($FF - K) Rd Rd + 1 Rd Rd - 1 Rd Rd * Rd Rd Rd Rd Rd $FF R1:R0 Rd x Rr R1:R0 Rd x Rr R1:R0 Rd x Rr R1:R0 (Rd x Rr) << 1 R1:R0 (Rd x Rr) << 1 R1:R0 (Rd x Rr) << 1 PC PC + k + 1 PC Z PC k PC PC + k + 1 PC Z PC k PC STACK PC STACK if (Rd = Rr) PC PC + 2 or 3 Rd - Rr Rd - Rr - C Rd - K if (Rr(b)=0) PC PC + 2 or 3 if (Rr(b)=1) PC PC + 2 or 3 if (P(b)=0) PC PC + 2 or 3 if (P(b)=1) PC PC + 2 or 3 if (SREG(s) = 1) then PCPC+k + 1 if (SREG(s) = 0) then PCPC+k + 1 if (Z = 1) then PC PC + k + 1 if (Z = 0) then PC PC + k + 1 if (C = 1) then PC PC + k + 1 if (C = 0) then PC PC + k + 1 if (C = 0) then PC PC + k + 1 if (C = 1) then PC PC + k + 1 if (N = 1) then PC PC + k + 1 if (N = 0) then PC PC + k + 1 if (N V= 0) then PC PC + k + 1 if (N V= 1) then PC PC + k + 1 if (H = 1) then PC PC + k + 1 if (H = 0) then PC PC + k + 1 if (T = 1) then PC PC + k + 1 if (T = 0) then PC PC + k + 1 if (V = 1) then PC PC + k + 1 if (V = 0) then PC PC + k + 1 Flags Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,C,N,V Z,C,N,V,H Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V None Z,C Z,C Z,C Z,C Z,C Z,C None None None None None None None I None Z, N,V,C,H Z, N,V,C,H Z, N,V,C,H None None None None None None None None None None None None None None None None None None None None None None #Clocks 1 1 2 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 3 3 3 4 4 4 1/2/3 1 1 1 1/2/3 1/2/3 1/2/3 1/2/3 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 ARITHMETIC AND LOGIC INSTRUCTIONS ADD Rd, Rr Add two Registers ADC Rd, Rr Add with Carry two Registers ADIW Rdl,K Add Immediate to Word SUB Rd, Rr Subtract two Registers SUBI Rd, K Subtract Constant from Register SBC Rd, Rr Subtract with Carry two Registers SBCI Rd, K Subtract with Carry Constant from Reg. SBIW Rdl,K Subtract Immediate from Word AND Rd, Rr Logical AND Registers ANDI Rd, K Logical AND Register and Constant OR Rd, Rr Logical OR Registers ORI Rd, K Logical OR Register and Constant EOR Rd, Rr Exclusive OR Registers COM Rd One's Complement NEG Rd Two's Complement SBR Rd,K Set Bit(s) in Register CBR Rd,K Clear Bit(s) in Register INC Rd Increment DEC Rd Decrement TST Rd Test for Zero or Minus CLR Rd Clear Register SER Rd Set Register MUL Rd, Rr Multiply Unsigned MULS Rd, Rr Multiply Signed MULSU Rd, Rr Multiply Signed with Unsigned FMUL Rd, Rr Fractional Multiply Unsigned FMULS Rd, Rr Fractional Multiply Signed FMULSU Rd, Rr Fractional Multiply Signed with Unsigned BRANCH INSTRUCTIONS RJMP k Relative Jump IJMP Indirect Jump to (Z) JMP k Direct Jump RCALL k Relative Subroutine Call ICALL Indirect Call to (Z) CALL k Direct Subroutine Call RET Subroutine Return RETI Interrupt Return CPSE Rd,Rr Compare, Skip if Equal CP Rd,Rr Compare CPC Rd,Rr Compare with Carry CPI Rd,K Compare Register with Immediate SBRC Rr, b Skip if Bit in Register Cleared SBRS Rr, b Skip if Bit in Register is Set SBIC P, b Skip if Bit in I/O Register Cleared SBIS P, b Skip if Bit in I/O Register is Set BRBS s, k Branch if Status Flag Set BRBC s, k Branch if Status Flag Cleared BREQ k Branch if Equal BRNE k Branch if Not Equal BRCS k Branch if Carry Set BRCC k Branch if Carry Cleared BRSH k Branch if Same or Higher BRLO k Branch if Lower BRMI k Branch if Minus BRPL k Branch if Plus BRGE k Branch if Greater or Equal, Signed BRLT k Branch if Less Than Zero, Signed BRHS k Branch if Half Carry Flag Set BRHC k Branch if Half Carry Flag Cleared BRTS k Branch if T Flag Set BRTC k Branch if T Flag Cleared BRVS k Branch if Overflow Flag is Set BRVC k Branch if Overflow Flag is Cleared 174 ATMEGA163(L) 1142E-AVR-02/03 ATMEGA163(L) Instruction Set Summary (Continued) BRIE k BRID k DATA TRANSFER INSTRUCTIONS MOV Rd, Rr MOVW Rd, Rr LDI Rd, K LD Rd, X LD Rd, X+ LD Rd, - X LD Rd, Y LD Rd, Y+ LD Rd, - Y LDD Rd,Y+q LD Rd, Z LD Rd, Z+ LD Rd, -Z LDD Rd, Z+q LDS Rd, k ST X, Rr ST X+, Rr ST - X, Rr ST Y, Rr ST Y+, Rr ST - Y, Rr STD Y+q,Rr ST Z, Rr ST Z+, Rr ST -Z, Rr STD Z+q,Rr STS k, Rr LPM LPM Rd, Z LPM Rd, Z+ SPM IN Rd, P OUT P, Rr PUSH Rr POP Rd BIT AND BIT-TEST INSTRUCTIONS SBI P,b CBI P,b LSL Rd LSR Rd ROL Rd ROR Rd ASR Rd SWAP Rd BSET s BCLR s BST Rr, b BLD Rd, b SEC CLC SEN CLN SEZ CLZ SEI CLI SES CLS SEV CLV SET CLT SEH Branch if Interrupt Enabled Branch if Interrupt Disabled Move Between Registers Copy Register Word Load Immediate Load Indirect Load Indirect and Post-Inc. Load Indirect and Pre-Dec. Load Indirect Load Indirect and Post-Inc. Load Indirect and Pre-Dec. Load Indirect with Displacement Load Indirect Load Indirect and Post-Inc. Load Indirect and Pre-Dec. Load Indirect with Displacement Load Direct from SRAM Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Store Indirect with Displacement Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Store Indirect with Displacement Store Direct to SRAM Load Program Memory Load Program Memory Load Program Memory and Post-Inc Store Program Memory In Port Out Port Push Register on Stack Pop Register from Stack Set Bit in I/O Register Clear Bit in I/O Register Logical Shift Left Logical Shift Right Rotate Left Through Carry Rotate Right Through Carry Arithmetic Shift Right Swap Nibbles Flag Set Flag Clear Bit Store from Register to T Bit load from T to Register Set Carry Clear Carry Set Negative Flag Clear Negative Flag Set Zero Flag Clear Zero Flag Global Interrupt Enable Global Interrupt Disable Set Signed Test Flag Clear Signed Test Flag Set Twos Complement Overflow. Clear Twos Complement Overflow Set T in SREG Clear T in SREG Set Half Carry Flag in SREG if ( I = 1) then PC PC + k + 1 if ( I = 0) then PC PC + k + 1 Rd Rr Rd+1:Rd Rr+1:Rr Rd K Rd (X) Rd (X), X X + 1 X X - 1, Rd (X) Rd (Y) Rd (Y), Y Y + 1 Y Y - 1, Rd (Y) Rd (Y + q) Rd (Z) Rd (Z), Z Z+1 Z Z - 1, Rd (Z) Rd (Z + q) Rd (k) (X) Rr (X) Rr, X X + 1 X X - 1, (X) Rr (Y) Rr (Y) Rr, Y Y + 1 Y Y - 1, (Y) Rr (Y + q) Rr (Z) Rr (Z) Rr, Z Z + 1 Z Z - 1, (Z) Rr (Z + q) Rr (k) Rr R0 (Z) Rd (Z) Rd (Z), Z Z+1 (Z) R1:R0 Rd P P Rr STACK Rr Rd STACK I/O(P,b) 1 I/O(P,b) 0 Rd(n+1) Rd(n), Rd(0) 0 Rd(n) Rd(n+1), Rd(7) 0 Rd(0)C,Rd(n+1) Rd(n),CRd(7) Rd(7)C,Rd(n) Rd(n+1),CRd(0) Rd(n) Rd(n+1), n=0..6 Rd(3..0)Rd(7..4),Rd(7..4)Rd(3..0) SREG(s) 1 SREG(s) 0 T Rr(b) Rd(b) T C1 C0 N1 N0 Z1 Z0 I1 I0 S1 S0 V1 V0 T1 T0 H1 None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None Z,C,N,V Z,C,N,V Z,C,N,V Z,C,N,V Z,C,N,V None SREG(s) SREG(s) T None C C N N Z Z I I S S V V T T H 1/2 1/2 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 3 3 1 1 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 175 1142E-AVR-02/03 Instruction Set Summary (Continued) CLH NOP SLEEP WDR Clear Half Carry Flag in SREG No Operation Sleep Watchdog Reset H0 (see specific descr. for Sleep function) (see specific descr. for WDR/timer) H None None None 1 1 1 1 176 ATMEGA163(L) 1142E-AVR-02/03 ATMEGA163(L) Ordering Information Speed (MHz) 4 Power Supply 2.7 - 5.5V Ordering Code ATMEGA163L-4AC ATMEGA163L-4PC ATMEGA163L-4AI ATMEGA163L-4PI 8 4.0 - 5.5V ATMEGA163-8AC ATMEGA163-8PC ATMEGA163-8AI ATMEGA163-8PI Package 44A 40P6 44A 40P6 44A 40P6 44A 40P6 Operation Range Commercial (0C to 70C) Industrial (-40C to 85C) Commercial (0C to 70C) Industrial (-40C to 85C) Package Type 44A 40P6 44-lead, Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP) 40-lead, 0.600" Wide, Plastic Dual Inline Package (PDIP) 177 1142E-AVR-02/03 Packaging Information 44A PIN 1 B PIN 1 IDENTIFIER e E1 E D1 D C 0~7 A1 L COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL A A1 A2 D D1 E MIN - 0.05 0.95 11.75 9.90 11.75 9.90 0.30 0.09 0.45 NOM - - 1.00 12.00 10.00 12.00 10.00 - - - 0.80 TYP MAX 1.20 0.15 1.05 12.25 10.10 12.25 10.10 0.45 0.20 0.75 Note 2 Note 2 NOTE A2 A Notes: 1. This package conforms to JEDEC reference MS-026, Variation ACB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10 mm maximum. E1 B C L e 10/5/2001 2325 Orchard Parkway San Jose, CA 95131 TITLE 44A, 44-lead, 10 x 10 mm Body Size, 1.0 mm Body Thickness, 0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) DRAWING NO. REV. 44A B R 178 ATMEGA163(L) 1142E-AVR-02/03 ATMEGA163(L) 40P6 D PIN 1 E1 A SEATING PLANE L B1 e E B A1 C eB 0 ~ 15 REF SYMBOL A A1 D E E1 B COMMON DIMENSIONS (Unit of Measure = mm) MIN - 0.381 52.070 15.240 13.462 0.356 1.041 3.048 0.203 15.494 NOM - - - - - - - - - - 2.540 TYP MAX 4.826 - 52.578 Note 2 15.875 13.970 Note 2 0.559 1.651 3.556 0.381 17.526 NOTE Notes: 1. This package conforms to JEDEC reference MS-011, Variation AC. 2. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm (0.010"). B1 L C eB e 09/28/01 2325 Orchard Parkway San Jose, CA 95131 TITLE 40P6, 40-lead (0.600"/15.24 mm Wide) Plastic Dual Inline Package (PDIP) DRAWING NO. REV. 40P6 B R 179 1142E-AVR-02/03 Erratas ATMEGA163(L) Errata Rev. F * * * * * * Increased Interrupt Latency Interrupts Abort TWI Power-down TWI Master Does not Accept Spikes on Bus Lines TWCR Write Operations Ignored PWM not Phase Correct TWI is Speed Limited in Slave Mode 6. Increased Interrupt Latency In this device, some instructions are not interruptable, and will cause the interrupt latency to increase. The only practical problem concerns a loop followed by a twoword instruction while waiting for an interrupt. The loop may consist of a branch instruction or an absolute or relative jump back to itself like this: loop: rjmp loop In this case, a dead-lock situation arises. Problem Fix/Workaround In assembly, insert a nop instruction immediately after a loop to itself. The problem will normally be detected during development. In C, the only construct that will give this problem is an empty "for" loop; "for(;;)". Use "while(1)" or "do{} while (1)" to avoid the problem. 5. Interrupts Abort TWI Power-down TWI Power-down operation may be aborted by other interrupts. If an interrupt (e.g., INT0) occurs during TWI Power-down address watch and wakes the CPU up, the TWI aborts operation and returns to its idle state. Problem Fix/Workaround Ensure that the TWI Address Match is the only enabled interrupt when entering Power-down. 4. TWI Master Does not Accept Spikes on Bus Lines When the part operates as Master, and the bus is idle (SDA = 1; SCL = 1), generating a short spike on SDA (SDA = 0 for a short interval), no interrupt is generated, and the status code is still $F8 (idle). But when the software initiates a new start condition and clears TWINT, nothing happens on SDA or SCL, and TWINT is never set again. Problem Fix/Workaround Either of the following: 1. Ensure that no spikes occur on SDA or SCL lines. 2. Receiving a valid START condition followed by a STOP condition provokes a bus error reported as a TWI interrupt with status code $00. 3. In a Single Master systems, the user should write the TWSTO bit immediately before writing the TWSTA bit. 3. TWCR Write Operation Ignored Repeated write to TWCR must be delayed. If a write operation to TWCR is immediately followed by another write operation to TWCR, the first write operation may be ignored. 180 ATMEGA163(L) 1142E-AVR-02/03 ATMEGA163(L) Problem Fix/Workaround Ensure at least one instruction (e.g., nop) is executed between two writes to TWCR. 2. PWM not Phase Correct In Phase-correct PWM mode, a change from OCRx = TOP to anything less than TOP does not change the OCx output. This gives a phase error in the following period. Problem Fix/Workaround Make sure this issue is not harmful to the application. 1. TWI is Speed Limited in Slave Mode When the two-wire Serial Interface operates in Slave mode, frames may be undetected if the CPU frequency is less than 64 times the bus frequency. Problem Fix/Workaround Ensure that the CPU frequency is at least 64 times the TWI bus frequency. 181 1142E-AVR-02/03 Change Log Changes from Rev. 1142C-09/01 to Rev. 1142D-09/02 Changes from Rev. 1142D-09/09 to Rev. 1142E-02/03 This section containes a log on the changes made to the data sheet for ATMEGA163. All refereces to pages in Change Log, are referred to this document. 1. Added "Not Recommend for New Designs. Use ATmega16.". 1. Updated Table 52, "Boot Reset Fuse," on page 136. 2. Corrected pin numbers in Figure 62 on page 113. 3. Corrected a constant in the Boot Loader code example on page 141. 4. Changed max bit rate for the TWI from 400 kHz to 217 kHz. 5. Removed redundant and harmful loop in a code example for Slave Receiver mode for the TWI on page 96. 6. Added AGND and AVCC in Figure 81 on page 145 and Figure 86 on page 154. 7. Updated the "Packaging Information" on page 178. 8. Added "Erratas" on page 180. 182 ATMEGA163(L) 1142E-AVR-02/03 ATMEGA163(L) Table of Contents Features................................................................................................. 1 Pin Configurations................................................................................ 2 Description ............................................................................................ 3 Block Diagram....................................................................................... 3 Pin Descriptions.................................................................................................... 4 Clock Options ....................................................................................................... 5 Timer Oscillator..................................................................................................... 6 Architectural Overview......................................................................... 7 The General Purpose Register File .................................................................... The ALU - Arithmetic Logic Unit......................................................................... The In-System Self-Programmable Flash Program Memory.............................. The SRAM Data Memory.................................................................................... The Program and Data Addressing Modes ........................................................ The EEPROM Data Memory .............................................................................. Memory Access Times and Instruction Execution Timing .................................. I/O Memory ......................................................................................................... Reset and Interrupt Handling .............................................................................. Sleep Modes....................................................................................................... Calibrated Internal RC Oscillator ........................................................................ 10 11 11 11 12 16 16 17 21 35 37 Timer/Counters ................................................................................... 39 Timer/Counter Prescalers ................................................................................... 8-bit Timer/Counter0........................................................................................... 16-bit Timer/Counter1......................................................................................... 8-bit Timer/Counter 2 .......................................................................................... 39 40 42 51 Watchdog Timer.................................................................................. 60 EEPROM Read/Write Access............................................................. 62 Preventing EEPROM Corruption ........................................................................ 64 Serial Peripheral Interface - SPI........................................................ 65 SS Pin Functionality............................................................................................ 66 Data Modes ........................................................................................................ 67 UART.................................................................................................... 70 Data Transmission.............................................................................................. Data Reception ................................................................................................... UART Control ..................................................................................................... Double Speed Transmission............................................................................... 70 72 74 78 i 1142E-AVR-02/03 Two-wire Serial Interface (Byte Oriented) ........................................ 80 Two-wire Serial Interface Modes ........................................................................ Master Transmitter Mode.................................................................................... Master Receiver Mode........................................................................................ Slave Receiver Mode.......................................................................................... Slave Transmitter Mode...................................................................................... Miscellaneous States .......................................................................................... 85 86 86 87 88 88 The Analog Comparator................................................................... 102 Analog Comparator Multiplexed Input .............................................................. 104 Analog to Digital Converter ............................................................. 105 Feature List....................................................................................................... Operation .......................................................................................................... Prescaling and Conversion Timing ................................................................... ADC Noise Canceler Function .......................................................................... Scanning Multiple Channels ............................................................................. ADC Noise Canceling Techniques ................................................................... ADC Characteristics ......................................................................................... 105 106 107 109 113 113 114 I/O Ports............................................................................................. 115 Port A................................................................................................................ Port B................................................................................................................ Port C................................................................................................................ Port D................................................................................................................ 115 117 123 128 Memory Programming...................................................................... 134 Boot Loader Support......................................................................................... Self-Programming the Flash ............................................................................. Preventing Flash Corruption ............................................................................. Program and Data Memory Lock Bits............................................................... Fuse Bits........................................................................................................... Signature Bytes ................................................................................................ Calibration Byte ................................................................................................ Parallel Programming ....................................................................................... Parallel Programming Characteristics .............................................................. Serial Downloading ........................................................................................... Serial Programming Characteristics ................................................................. 134 136 141 143 144 144 144 145 153 154 159 Electrical Characteristics................................................................. 160 Absolute Maximum Ratings*............................................................................. 160 External Clock Drive Waveforms .................................................... 161 External Clock Drive......................................................................... 162 ii ATMEGA163(L) 1142E-AVR-02/03 ATMEGA163(L) Two-wire Serial Interface Characteristics ...................................... 163 Typical Characteristics .................................................................... 165 Register Summary ............................................................................ 172 Instruction Set Summary ................................................................. 174 Ordering Information........................................................................ 177 Packaging Information ..................................................................... 178 44A ................................................................................................................... 178 40P6 ................................................................................................................. 179 Erratas ............................................................................................... 180 ATMEGA163(L) Errata Rev. F ........................................................................... 180 Change Log ....................................................................................... 182 Changes from Rev. 1142C-09/01 to Rev. 1142D-09/02................................... 182 Changes from Rev. 1142D-09/09 to Rev. 1142E-02/03 ................................... 182 Table of Contents .................................................................................. i iii 1142E-AVR-02/03 iv ATMEGA163(L) 1142E-AVR-02/03 Atmel Headquarters Corporate Headquarters 2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 441-0311 FAX 1(408) 487-2600 Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 441-0311 FAX 1(408) 436-4314 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany TEL (49) 71-31-67-0 FAX (49) 71-31-67-2340 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TEL 1(719) 576-3300 FAX 1(719) 540-1759 Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland TEL (41) 26-426-5555 FAX (41) 26-426-5500 Microcontrollers 2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 441-0311 FAX 1(408) 436-4314 La Chantrerie BP 70602 44306 Nantes Cedex 3, France TEL (33) 2-40-18-18-18 FAX (33) 2-40-18-19-60 Biometrics/Imaging/Hi-Rel MPU/ High Speed Converters/RF Datacom Avenue de Rochepleine BP 123 38521 Saint-Egreve Cedex, France TEL (33) 4-76-58-30-00 FAX (33) 4-76-58-34-80 Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimhatsui East Kowloon Hong Kong TEL (852) 2721-9778 FAX (852) 2722-1369 ASIC/ASSP/Smart Cards Zone Industrielle 13106 Rousset Cedex, France TEL (33) 4-42-53-60-00 FAX (33) 4-42-53-60-01 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TEL 1(719) 576-3300 FAX 1(719) 540-1759 Scottish Enterprise Technology Park Maxwell Building East Kilbride G75 0QR, Scotland TEL (44) 1355-803-000 FAX (44) 1355-242-743 Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan TEL (81) 3-3523-3551 FAX (81) 3-3523-7581 literature@atmel.com Web Site http://www.atmel.com (c) Atmel Corporation 2003. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Atmel's Terms and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel's products are not authorized for use as critical components in life support devices or systems. ATMEL (R) and AVR (R) are the registered trademarks of Atmel. Other terms and product names may be the trademarks of others. Printed on recycled paper. 1142E-AVR-02/03 0M |
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